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Thurs build #277

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Thurs build #277

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79be45d
initial look around
Apr 13, 2021
552ae6b
what I have so far w/o additional notes
Apr 13, 2021
481a7d4
added file loader
Apr 14, 2021
17ab9a8
MUL added
Apr 14, 2021
5b03de1
push and pop added
Apr 15, 2021
266fda2
Call and RET added
Apr 16, 2021
a38c610
instruction binary added
Apr 16, 2021
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Call and RET added
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Simone Ballard committed Apr 16, 2021
commit 266fda20f5031cbf2ac0b3510602fc047af8c423
18 changes: 16 additions & 2 deletions ls8/cpu.py
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
MUL = 0b10100010
PUSH = 8
POP = 10
CALL = 11
RET = 12

class CPU:
"""Main CPU class."""
Expand Down Expand Up @@ -114,7 +116,7 @@ def run(self):
self.alu("MUL", self.reg_a, self.reg_b)
#PUSH
elif instruction == PUSH:
reg_index = self.ram[self.pc + 1]
reg_index = operand_a
val = self.registers[reg_index]

self.registers[self.sp] -= 1
Expand All @@ -123,7 +125,7 @@ def run(self):
self.pc += 2
#POP
elif instruction == POP:
reg_index = self.ram[self.pc + 1]
reg_index = operand_a

self.registers[reg_index] = self.ram[self.registers[self.sp]]

Expand All @@ -133,6 +135,18 @@ def run(self):
elif instruction == HLT:
running = False
sys.exit(0)
# CALL
elif instruction == CALL:
address_to_return_to = self.pc + 2
self.registers[self.pc] -= 1
self.ram[self.registers[self.sp]] = address_to_return_to
reg_index = operand_a
address_to_call = self.registers[reg_index]
self.pc = address_to_call

elif instruction == RET:
self.pc = self.ram[self.registers[self.sp]]
self.registers[self.sp] + 1

else:
print("WRONG WAY")
Expand Down