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Merge branch 'update-cluster-interconnect-rebase-balasr' into 'master'
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Update pulp_cluster interconnect

# **Merge queue**

After !56, this branch root source

# **Overview**

This PR upgrades pulp_cluster interconnects aligning with the new version recently introduced in [pulp-open](pulp-platform/pulp#49) (still not in master).

# **Checklist**

- [x] Bump version of several cluster IPs (`pulp_cluster`, `icache_mp_128_pf`, `hier-icache`, `cluster_peripherals`, `cluster_interconnect`, `mchan`)
- [x] Bump `axi` to v0.28.0 
- [x] Glue the updated IP with control_pulp hw
- [x] Update CHANGELOG with more detailed information on IP bump versions and cluster interconnect changes
- [x] Adopt novel AXI clock domain crossing setup in the cluster-soc communication (required `axi >= v0.28.0`)
- [x] Adopt the use of 32-bit private icache to prevent issues arisen with Mobilenet workload in pulp-open (test still to be included here)

# **Fixes**

Fixes pulp-platform#22 

# **Notes** 

~~- I wasn't able to properly `git subtree pull` the `axi` repo. A lot of (unexpected) conflicts arised. To shorten the process, I removed the axi IP directory and called `git subtree add` again. This should not have implications on the history itself. Yet it is a bit of a ugly solution, but I hope non-blocking for the merge. 
Otherwise, we can figure out alternatives by rebasing~~

~~- I was able to bump some IPs without the `--squash` option only, perhaps because they were added in that flatten way originally as well. Again, hope this is not a blocking issue~~

**NB** Previous notes were fixed by workarounding `git subtree pull` command

See merge request balasr/control-pulp!67
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@bluewww
bluewww committed Jun 25, 2021
2 parents 2932653 + 065003c commit cbee72c
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Showing 12 changed files with 1,237 additions and 1,293 deletions.
12 changes: 10 additions & 2 deletions packages/pulp_cluster_package.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,13 @@

package pulp_cluster_package;

typedef struct packed {
logic [31:0] idx;
logic [31:0] start_addr;
logic [31:0] end_addr;
} addr_map_rule_t;


parameter NB_SPERIPH_PLUGS_EU = 2;


Expand All @@ -32,8 +39,9 @@ package pulp_cluster_package;
parameter SPER_DMA_CL_ID = 6;
parameter SPER_DMA_FC_ID = 7;
parameter SPER_DECOMP_ID = 8;
parameter SPER_EXT_ID = 9;

parameter SPER_EXT_ID = 9; // HAS to be the last one
parameter SPER_ERROR_ID = 10;

// if set to 1, then instantiate APU in the cluster
// parameter APU_CLUSTER = 0;

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472 changes: 127 additions & 345 deletions rtl/cluster_bus_wrap.sv
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5 changes: 1 addition & 4 deletions rtl/cluster_event_map.sv
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Expand Up @@ -31,9 +31,6 @@ module cluster_event_map
input logic [NB_CORES-1:0][1:0] timer_events_i,
input logic [NB_CORES-1:0][31:0] cluster_events_i,

input logic decompr_done_evt_i,


output logic [NB_CORES-1:0][31:0] events_mapped_o
);

Expand All @@ -44,7 +41,7 @@ module cluster_event_map
assign events_mapped_o[I][31:28] = '0;
assign events_mapped_o[I][27] = periph_fifo_event_i;
assign events_mapped_o[I][26:25] = '0;
assign events_mapped_o[I][24] = decompr_done_evt_i;
assign events_mapped_o[I][24] = '0;
assign events_mapped_o[I][23:22] = cluster_events_i[I][1:0];
assign events_mapped_o[I][21:19] = '0;

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274 changes: 67 additions & 207 deletions rtl/cluster_interconnect_wrap.sv
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171 changes: 82 additions & 89 deletions rtl/cluster_peripherals.sv
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Expand Up @@ -52,7 +52,7 @@ module cluster_peripherals

output logic busy_o,

XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0],
XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0], // SPER_EXT_ID NOT PLUGGED HERE
XBAR_PERIPH_BUS.Slave core_eu_direct_link[NB_CORES-1:0],

//input logic [NB_CORES-1:0] dma_events_i,
Expand All @@ -63,8 +63,6 @@ module cluster_peripherals
input logic dma_cl_irq_i,
//input logic dma_pe_irq_i,
//output logic pf_event_o,

//input logic decompr_done_evt_i,

input logic dma_fc_event_i,
input logic dma_fc_irq_i,
Expand Down Expand Up @@ -95,25 +93,27 @@ module cluster_peripherals
XBAR_PERIPH_BUS.Master hwpe_cfg_master,
input logic [NB_CORES-1:0][3:0] hwpe_events_i,
output logic hwpe_sel_o,
output logic hwpe_en_o,
output logic hwpe_en_o

//output logic [NB_L1_CUTS-1:0][RW_MARGIN_WIDTH-1:0] rw_margin_L1_o,

// Control ports
`ifdef PRIVATE_ICACHE
SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS],
PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES],
output logic special_core_icache_cfg_o,
output logic enable_l1_l15_prefetch_o
,
SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS],
PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES],
output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o
`else
`ifdef SP_ICACHE
// Control ports
SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus[NB_CACHE_BANKS],
L0_CTRL_UNIT_BUS.Master L0_ctrl_unit_bus[NB_CORES]
,
// Control ports
SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus[NB_CACHE_BANKS],
L0_CTRL_UNIT_BUS.Master L0_ctrl_unit_bus[NB_CORES]
`else
`ifdef MP_ICACHE
MP_PF_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus
`endif
`ifdef MP_ICACHE
,
MP_PF_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus
`endif
`endif
`endif

Expand Down Expand Up @@ -145,6 +145,12 @@ module cluster_peripherals

// internal speriph bus to combine multiple plugs to new event unit
XBAR_PERIPH_BUS speriph_slave_eu_comb();

`ifdef FEATURE_ICACHE_STAT
localparam bit FEATURE_STAT = 1'b1;
`else
localparam bit FEATURE_STAT = 1'b0;
`endif

// decide between common or core-specific event sources
generate
Expand Down Expand Up @@ -233,29 +239,17 @@ module cluster_peripherals
assign eu_message_master.r_opc = 1'b0;
assign eu_message_master.gnt = 1'b1;

// combine number of required slave ports for event unit
// With new interconnect xbar_pe, all requests to EU pass through SPER_EVENT_U_ID speriph_slave. The other plugs are tied to 0.
generate
for (genvar I = 0; I < NB_SPERIPH_PLUGS_EU; I++ ) begin
assign speriph_slave[SPER_EVENT_U_ID+I].gnt = speriph_slave_eu_comb.gnt;
assign speriph_slave[SPER_EVENT_U_ID+I].r_valid = speriph_slave_eu_comb.r_valid;
assign speriph_slave[SPER_EVENT_U_ID+I].r_opc = speriph_slave_eu_comb.r_opc;
assign speriph_slave[SPER_EVENT_U_ID+I].r_id = speriph_slave_eu_comb.r_id;
assign speriph_slave[SPER_EVENT_U_ID+I].r_rdata = speriph_slave_eu_comb.r_rdata;
assign eu_speriph_plug_req[I] = speriph_slave[SPER_EVENT_U_ID+I].req;
assign eu_speriph_plug_add[I] = speriph_slave[SPER_EVENT_U_ID+I].add;
assign eu_speriph_plug_wen[I] = speriph_slave[SPER_EVENT_U_ID+I].wen;
assign eu_speriph_plug_wdata[I] = speriph_slave[SPER_EVENT_U_ID+I].wdata;
assign eu_speriph_plug_be[I] = speriph_slave[SPER_EVENT_U_ID+I].be;
assign eu_speriph_plug_id[I] = speriph_slave[SPER_EVENT_U_ID+I].id;
for (genvar I = 1; I < NB_SPERIPH_PLUGS_EU; I++ ) begin
assign speriph_slave[SPER_EVENT_U_ID+I].gnt = '0;
assign speriph_slave[SPER_EVENT_U_ID+I].r_valid = '0;
assign speriph_slave[SPER_EVENT_U_ID+I].r_opc = '0;
assign speriph_slave[SPER_EVENT_U_ID+I].r_id = '0;
assign speriph_slave[SPER_EVENT_U_ID+I].r_rdata = 32'hDEADB33F;
end
endgenerate

assign speriph_slave_eu_comb.req = |eu_speriph_plug_req;
assign speriph_slave_eu_comb.add = (eu_speriph_plug_req == 2'b10) ? eu_speriph_plug_add[1] : eu_speriph_plug_add[0];
assign speriph_slave_eu_comb.wen = (eu_speriph_plug_req == 2'b10) ? eu_speriph_plug_wen[1] : eu_speriph_plug_wen[0];
assign speriph_slave_eu_comb.wdata = (eu_speriph_plug_req == 2'b10) ? eu_speriph_plug_wdata[1] : eu_speriph_plug_wdata[0];
assign speriph_slave_eu_comb.be = (eu_speriph_plug_req == 2'b10) ? eu_speriph_plug_be[1] : eu_speriph_plug_be[0];
assign speriph_slave_eu_comb.id = (eu_speriph_plug_req == 2'b10) ? eu_speriph_plug_id[1] : eu_speriph_plug_id[0];


event_unit_top #(
Expand All @@ -270,7 +264,6 @@ module cluster_peripherals

.acc_events_i ( s_acc_events ),
.dma_events_i ( s_dma_events ),
.decompr_done_evt_i ( '0 ), //decompr_done_evt_i
.timer_events_i ( s_timer_events ),
.cluster_events_i ( s_cluster_events ),

Expand All @@ -286,7 +279,7 @@ module cluster_peripherals
.core_busy_i ( core_busy_i ),
.core_clock_en_o ( core_clk_en_o ),

.speriph_slave ( speriph_slave_eu_comb ),
.speriph_slave ( speriph_slave[SPER_EVENT_U_ID] ),
.eu_direct_link ( core_eu_direct_link ),

.soc_periph_evt_valid_i ( soc_periph_evt_valid_i ),
Expand All @@ -304,63 +297,63 @@ module cluster_peripherals


`ifdef PRIVATE_ICACHE //to be integrated hier_icache


hier_icache_ctrl_unit_wrap
#(
.NB_CACHE_BANKS(NB_CACHE_BANKS),
.NB_CORES(NB_CORES),
.ID_WIDTH(NB_CORES+NB_MPERIPHS)
)
icache_ctrl_unit_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

.speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ),
.IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ),
.IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ),
.special_core_icache_cfg_o ( special_core_icache_cfg_o ), //special_core_icache_cfg_o
.enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o )
);



hier_icache_ctrl_unit_wrap
#(
.NB_CACHE_BANKS(NB_CACHE_BANKS),
.NB_CORES(NB_CORES),
.ID_WIDTH(NB_CORES+NB_MPERIPHS)
)
icache_ctrl_unit_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

.speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ),
.IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ),
.IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ),
.enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o )
);

`else
`ifdef MP_ICACHE
mp_pf_icache_ctrl_unit
#(
.NB_CACHE_BANKS(NB_CACHE_BANKS),
.NB_CORES(NB_CORES),
.ID_WIDTH(NB_CORES+NB_MPERIPHS)
)
icache_ctrl_unit_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

.speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ),
.IC_ctrl_unit_master_if ( IC_ctrl_unit_bus ),
.pf_event_o ( )
`ifdef MP_ICACHE
mp_pf_icache_ctrl_unit
#(
.NB_CACHE_BANKS ( NB_CACHE_BANKS ),
.NB_CORES ( NB_CORES ),
.ID_WIDTH ( NB_CORES+NB_MPERIPHS ),
.FEATURE_STAT ( FEATURE_STAT )
)
icache_ctrl_unit_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

.speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ),
.IC_ctrl_unit_master_if ( IC_ctrl_unit_bus ),
.pf_event_o ( )
);
`else
`ifdef SP_ICACHE
sp_icache_ctrl_unit
#(
.NB_CACHE_BANKS ( NB_CACHE_BANKS ),
.NB_CORES ( NB_CORES ),
.ID_WIDTH ( NB_CORES+NB_MPERIPHS ),
.OFFSET ( 4 ),
.FEATURE_STAT ( FEATURE_STAT )
)
icache_ctrl_unit_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

.speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ),
.IC_ctrl_unit_master_if ( IC_ctrl_unit_bus ),
.L0_ctrl_unit_master_if ( L0_ctrl_unit_bus )
);
`else
`ifdef SP_ICACHE
sp_icache_ctrl_unit
#(
.NB_CACHE_BANKS(NB_CACHE_BANKS),
.NB_CORES(NB_CORES),
.ID_WIDTH(NB_CORES+NB_MPERIPHS)
)
icache_ctrl_unit_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

.speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ),
.IC_ctrl_unit_master_if ( IC_ctrl_unit_bus ),
.L0_ctrl_unit_master_if ( L0_ctrl_unit_bus )
);
`endif
`endif
`endif
`endif

//********************************************************
Expand Down
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