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hardware CTS and RTS working and tested #126

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hardware CTS and RTS working and tested #126

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0e8977a
hardware CTS and RTS working and tested
S0urceror Dec 12, 2023
cc40899
full-duplex mode is signalled by PACKET_GP > 1
S0urceror Jan 9, 2024
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3 changes: 2 additions & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
Debug/
Release/
Release/
.DS_Store
26 changes: 26 additions & 0 deletions MOS.wsp
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Original file line number Diff line number Diff line change
Expand Up @@ -4,3 +4,29 @@ ptn_Child1=Frames
[WorkState_v1_2.Frames]
ptn_Child1=ChildFrames

[WorkState_v1_2.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1

[WorkState_v1_2.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0

[WorkState_v1_2.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=src\uart.c
DocTemplateIndex=0
DocumentString=IDE.Document
IsActiveChildFrame=False
IsFrameVisible=True
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPIPPPPPPPBOPPPPPPOEAAAAAAOEAAAAAAJCFAAAAABLBAAAAA

[WorkState_v1_2.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0

[WorkState_v1_2.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=.\main.c
DocTemplateIndex=0
DocumentString=IDE.Document
IsActiveChildFrame=True
IsFrameVisible=True
WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPIPPPPPPPBOPPPPPPIGAAAAAAIGAAAAAAHEFAAAAAPMBAAAAA

2 changes: 1 addition & 1 deletion main.c
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Expand Up @@ -82,7 +82,7 @@ int wait_ESP32(UART * pUART, UINT24 baudRate) {
putch(23); // Send a general poll packet
putch(0);
putch(VDP_gp);
putch(1);
putch(2); // 2 = full-duplex-mode, 1 = half-duplex-mode (default)
for(i = 0; i < 5; i++) { // Wait 50ms
wait_timer0();
}
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5 changes: 3 additions & 2 deletions src/serial.asm
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Expand Up @@ -75,8 +75,9 @@ UART_LSR_RDY EQU %01 ; Data ready

; Check whether we're clear to send (UART0 only)
;
UART0_wait_CTS: GET_GPIO PD_DR, 8 ; Check Port D, bit 3 (CTS)
JR NZ, UART0_wait_CTS
UART0_wait_CTS: in0 a, (UART0_REG_MSR)
bit 4,a ; check inverted CTS bit, 1 = CTS, 0 = NOT CTS (clear to send)
JR Z, UART0_wait_CTS
RET

UART1_wait_CTS: GET_GPIO PC_DR, 8 ; Check Port C, bit 3 (CTS)
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8 changes: 4 additions & 4 deletions src/uart.c
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Expand Up @@ -74,17 +74,17 @@ BYTE open_UART0(UART * pUART) {
SETREG(PD_ALT2, pins);

if(pUART->flowControl == FCTL_HW) {
SETREG(PD_DDR, PORTPIN_THREE); // Set Port D bit 3 (CTS) for input
RESETREG(PD_ALT1, PORTPIN_THREE);
RESETREG(PD_ALT2, PORTPIN_THREE);
SETREG(PD_DDR, PORTPIN_THREE|PORTPIN_TWO); // Set Port D bit 3 and 2 (CTS,RTS) to alternate function
RESETREG(PD_ALT1, PORTPIN_THREE|PORTPIN_TWO);
SETREG(PD_ALT2, PORTPIN_THREE|PORTPIN_TWO);
serialFlags |= 0x02;
}

UART0_LCTL |= UART_LCTL_DLAB; // Select DLAB to access baud rate generators
UART0_BRG_L = (br & 0xFF); // Load divisor low
UART0_BRG_H = (CHAR)(( br & 0xFF00 ) >> 8); // Load divisor high
UART0_LCTL &= (~UART_LCTL_DLAB); // Reset DLAB; dont disturb other bits
UART0_MCTL = 0x00; // Bring modem control register to reset value
UART0_MCTL = 0x02; // Multidrop, loopback, DTR disabled, RTS enabled
UART0_FCTL = 0x07; // Enable and clear hardware FIFOs
UART0_IER = pUART->interrupts; // Set interrupts

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