implement some quirks...

breqdev · Nov 17, 2023 · 2369b68 · 2369b68
1 parent 3669596
commit 2369b68
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Showing 2 changed files with 34 additions and 5 deletions.
diff --git a/src/cpu/execute.rs b/src/cpu/execute.rs
@@ -133,6 +133,7 @@ impl Execute for Mos6502 {
         // ASL
         let (address, cycles) = self.fetch_operand_address(opcode);
         let value = self.read(address);
+        self.write(address, value); // QUIRK
         let result = value << 1;
 
         self.registers.sr.write(flags::CARRY, value & 0x80 != 0);
@@ -154,6 +155,7 @@ impl Execute for Mos6502 {
         // LSR
         let (address, cycles) = self.fetch_operand_address(opcode);
         let value = self.read(address);
+        self.write(address, value); // QUIRK
         let result = value >> 1;
 
         self.registers.sr.write(flags::CARRY, value & 0x01 != 0);
@@ -176,6 +178,7 @@ impl Execute for Mos6502 {
         // ROL
         let (address, cycles) = self.fetch_operand_address(opcode);
         let value = self.read(address);
+        self.write(address, value); // QUIRK
         let result = (value << 1) | (self.registers.sr.read(flags::CARRY) as u8);
 
         self.registers.sr.write(flags::CARRY, value & 0x80 != 0);
@@ -198,6 +201,7 @@ impl Execute for Mos6502 {
         // ROR
         let (address, cycles) = self.fetch_operand_address(opcode);
         let value = self.read(address);
+        self.write(address, value); // QUIRK
         let result = value >> 1 | (self.registers.sr.read(flags::CARRY) as u8) << 7;
 
         self.registers.sr.write(flags::CARRY, value & 0x01 != 0);
@@ -341,7 +345,16 @@ impl Execute for Mos6502 {
           0x4C => (self.fetch_word(), 3),
           0x6C => {
             let indirect = self.fetch_word();
-            (self.read_word(indirect), 5)
+
+            // QUIRK
+            if indirect & 0xFF == 0xFF {
+              let lo = self.read(indirect);
+              let hi = self.read(indirect & 0xFF00);
+              ((hi as u16) << 8 | lo as u16, 5)
+            } else {
+              // normal behavior
+              (self.read_word(indirect), 5)
+            }
           }
           _ => unreachable!(),
         };

diff --git a/src/cpu/fetch.rs b/src/cpu/fetch.rs
@@ -88,15 +88,31 @@ impl Fetch for Mos6502 {
       0x1C | 0x1D => {
         // Absolute,X
         let base = self.fetch_word();
-        (base + self.registers.x as u16, 4)
+        let indexed = base + self.registers.x as u16;
+
+        // QUIRK
+        if base & 0xFF00 != indexed & 0xFF00 {
+          self.read(base & 0xFF00 | indexed & 0x00FF);
+          (indexed, 5)
+        } else {
+          (indexed, 4)
+        }
       }
       0x1E | 0x1F => {
         // Absolute,X or Absolute,Y
         let base = self.fetch_word();
-        if opcode & 0xC0 == 0x80 {
-          (base + self.registers.y as u16, 4)
+        let indexed = if opcode & 0xC0 == 0x80 {
+          base + self.registers.y as u16
+        } else {
+          base + self.registers.x as u16
+        };
+
+        // QUIRK
+        if base & 0xFF00 != indexed & 0xFF00 {
+          self.read(base & 0xFF00 | indexed & 0x00FF);
+          (indexed, 5)
         } else {
-          (base + self.registers.x as u16, 4)
+          (indexed, 4)
         }
       }
       _ => unreachable!(),