Icache4way

chip_top/AnyCore_Piton.sv

@@ -103,14 +103,15 @@ module AnyCore_Piton(
 
 wire [`ICACHE_BLOCK_ADDR_BITS-1:0] ic2memReqAddr;    // memory read address
 wire                               ic2memReqValid;   // memory read enable
+wire  [1:0]                        ic2memReqWay;     // memory way 
 wire [`ICACHE_TAG_BITS-1:0]        mem2icTag;        // tag of the incoming data
 wire [`ICACHE_INDEX_BITS-1:0]      mem2icIndex;      // index of the incoming data
 wire [`ICACHE_BITS_IN_LINE-1:0]    mem2icData;       // requested data
 wire                               mem2icRespValid;  // requested data is ready
 
 wire                               mem2icInv;        // icache invalidation
 wire  [`ICACHE_INDEX_BITS-1:0]     mem2icInvInd;     // icache invalidation index
-wire  [0:0]                        mem2icInvWay;     // icache invalidation way (unused)
+wire  [1:0]                        mem2icInvWay;     // icache invalidation way (unused)
 
 // cache-to-memory interface for Loads
 wire [`DCACHE_BLOCK_ADDR_BITS-1:0] dc2memLdAddr;  // memory read address
@@ -448,6 +449,7 @@ Core_OOO coreTop(
   `ifdef INST_CACHE
     .ic2memReqAddr_o                     (ic2memReqAddr  ),      // memory read address
     .ic2memReqValid_o                    (ic2memReqValid ),     // memory read enable
+    .ic2memReqWay_o                      (ic2memReqWay),
     .mem2icTag_i                         (mem2icTag      ),          // tag of the incoming data
     .mem2icIndex_i                       (mem2icIndex    ),        // index of the incoming data
     .mem2icData_i                        (mem2icData     ),         // requested data
@@ -586,6 +588,7 @@ Core_OOO coreTop(
 //`endif
 
 
+    //DO WE EVEN NEED TO ADD STUFF HERE?
     // not supported at the moment
     assign transducer_l15_amo_op = `L15_AMO_OP_NONE;
     anycore_tri_transducer tri_transducer(
@@ -597,6 +600,7 @@ Core_OOO coreTop(
 
         .ic2mem_reqaddr_i                  (ic2memReqAddr),
         .ic2mem_reqvalid_i                 (ic2memReqValid),
+        .ic2memReqWay_o                    (ic2memReqWay),
 
         .dc2mem_ldaddr_i                   (dc2memLdAddr),
         .dc2mem_ldvalid_i                  (dc2memLdValid),

chip_top/anycore_tri_transducer.v

@@ -10,6 +10,7 @@ module anycore_tri_transducer(
 
     input [`ICACHE_BLOCK_ADDR_BITS-1:0] ic2mem_reqaddr_i,
     input                               ic2mem_reqvalid_i,
+    output [1:0]                        ic2memReqWay_o,
 
     input [`DCACHE_BLOCK_ADDR_BITS-1:0] dc2mem_ldaddr_i,
 
@@ -58,6 +59,7 @@ module anycore_tri_transducer(
     input wire [1:0]    l15_transducer_cross_invalidate_way_i,
     input wire          l15_transducer_inval_dcache_inval_i,
     input wire          l15_transducer_inval_icache_inval_i,
+    //said something about this wire
     input wire [1:0]    l15_transducer_inval_way_i,
     input wire          l15_transducer_blockinitstore_i,
 
@@ -80,7 +82,7 @@ module anycore_tri_transducer(
 
     output                              mem2ic_invvalid_o,
     output [`ICACHE_INDEX_BITS-1:0]     mem2ic_invindex_o,
-    output [0:0]                        mem2ic_invway_o,
+    output [1:0]                        mem2ic_invway_o,
 
     input                               dc2mem_stvalid_i,
     output reg                          mem2dc_stcomplete_o,
@@ -98,7 +100,9 @@ reg header_ack_seen_reg;
 // Get full address that's 64 bits long since it's otherwise to icache
 // block alignment
 wire [63:0] anycore_imiss_full_addr = ic2mem_reqaddr_i << (64-`ICACHE_BLOCK_ADDR_BITS);
-wire [1:0] anycore_imiss_way = ic2mem_reqaddr_i[`ICACHE_INDEX_BITS-1:`ICACHE_INDEX_BITS-2-1];
+//CHANGES
+//wire [1:0] anycore_imiss_way = ic2mem_reqaddr_i[`ICACHE_INDEX_BITS-1:`ICACHE_INDEX_BITS-2-1];
+wire [1:0] anycore_imiss_way = ic2memReqWay_o;
 // Sign extend to 64 bits
 //wire [63:0] anycore_store_full_addr = {{((64-`DCACHE_ST_ADDR_BITS)-3){dc2mem_staddr_i[`DCACHE_ST_ADDR_BITS-1]}}, (dc2mem_staddr_i << 3)};
 wire [63:0] anycore_store_full_addr = {{((64-`DCACHE_ST_ADDR_BITS)-3){dc2mem_staddr_i[`DCACHE_ST_ADDR_BITS-1]}}, (dc2mem_staddr_i)};
@@ -411,9 +415,14 @@ end
 
 assign mem2dc_invvalid_o = signal_dcache_inval & ~dinvalrst_reg;
 assign mem2ic_invvalid_o = signal_icache_inval & ~iinvalrst_reg;
+//CHANGES
 assign mem2dc_invway_o = l15_transducer_inval_way_i;
+//assign mem2dc_invway_o = ic2memReqWay_o;
+//assign mem2dc_invway_o = mem2icInvWay_i;
 assign mem2dc_invindex_o = l15_transducer_inval_address_15_4_i[`DCACHE_INDEX_BITS+4-1:4];
-assign mem2ic_invway_o = l15_transducer_inval_way_i;
+//assign mem2ic_invway_o = 1; //l15_transducer_inval_way_i;
+assign mem2ic_invway_o = ic2memReqWay_o;
+//assign mem2ic_invway_o = mem2icInvWay_i;
 assign mem2ic_invindex_o = l15_transducer_inval_address_15_4_i[`DCACHE_INDEX_BITS+4-1:4];
 
 always @ * begin

core_top/Core_OOO.sv

@@ -54,14 +54,16 @@ module Core_OOO(
 `ifdef INST_CACHE
   output [`ICACHE_BLOCK_ADDR_BITS-1:0]ic2memReqAddr_o,      // memory read address
   output                              ic2memReqValid_o,     // memory read enable
+  output [1:0]  					  ic2memReqWay_o,
+
   input  [`ICACHE_TAG_BITS-1:0]       mem2icTag_i,          // tag of the incoming data
   input  [`ICACHE_INDEX_BITS-1:0]     mem2icIndex_i,        // index of the incoming data
   input  [`ICACHE_BITS_IN_LINE-1:0]   mem2icData_i,         // requested data
   input                               mem2icRespValid_i,    // requested data is ready
 
   input                               mem2icInv_i,          // icache invalidation
   input  [`ICACHE_INDEX_BITS-1:0]     mem2icInvInd_i,       // icache invalidation index
-  input  [0:0]                        mem2icInvWay_i,       // icache invalidation way (unused)
+  input  [1:0]                        mem2icInvWay_i,       // icache invalidation way (unused)
 
   //input                               instCacheBypass_i,
   input                               icScratchModeEn_i,    // Should ideally be disabled by default
@@ -501,6 +503,7 @@ FetchStage1 fs1(
 `ifdef INST_CACHE
   .ic2memReqAddr_o      (ic2memReqAddr_o     ),      // memory read address
   .ic2memReqValid_o     (ic2memReqValid_o    ),     // memory read enable
+  .ic2memReqWay_o       (ic2memReqWay_o      ),
   .mem2icTag_i          (mem2icTag_i         ),          // tag of the incoming data
   .mem2icIndex_i        (mem2icIndex_i       ),        // index of the incoming data
   .mem2icData_i         (mem2icData_i        ),         // requested data

fetch/FetchStage1.sv

@@ -38,14 +38,16 @@ module FetchStage1(
 `ifdef INST_CACHE
     output [`ICACHE_BLOCK_ADDR_BITS-1:0]ic2memReqAddr_o,     // memory read address
     output                           ic2memReqValid_o,     // memory read enable
+    output [1:0]                     ic2memReqWay_o,
+
     input  [`ICACHE_TAG_BITS-1:0]    mem2icTag_i,          // tag of the incoming data
     input  [`ICACHE_INDEX_BITS-1:0]  mem2icIndex_i,        // index of the incoming data
     input  [`ICACHE_BITS_IN_LINE-1:0]   mem2icData_i,         // requested data
     input                            mem2icRespValid_i,    // requested data is ready
 
     input                            mem2icInv_i,          // icache invalidation
     input  [`ICACHE_INDEX_BITS-1:0]  mem2icInvInd_i,       // icache invalidation index
-    input  [0:0]                     mem2icInvWay_i,       // icache invalidation way (unused)
+    input  [1:0]                     mem2icInvWay_i,       // icache invalidation way (unused)
 
     input                            icScratchModeEn_i,    // Should ideally be disabled by default
     input [`ICACHE_INDEX_BITS+`ICACHE_BYTES_IN_LINE_LOG-1:0]  icScratchWrAddr_i,
@@ -330,6 +332,7 @@ L1ICache l1icache(
 `ifdef INST_CACHE
     .ic2memReqAddr_o      (ic2memReqAddr_o     ),     // memory read address
     .ic2memReqValid_o     (ic2memReqValid_o    ),     // memory read enable
+    .ic2memReqWay_o       (ic2memReqWay_o      ),
     .mem2icTag_i          (mem2icTag_i         ),     // tag of the incoming data
     .mem2icIndex_i        (mem2icIndex_i       ),     // index of the incoming data
     .mem2icData_i         (mem2icData_i        ),     // requested data

fetch/L1ICache.sv

@@ -47,14 +47,16 @@ module L1ICache (
 `ifdef INST_CACHE
   output [`ICACHE_BLOCK_ADDR_BITS-1:0]  ic2memReqAddr_o,      // memory read address
   output                                ic2memReqValid_o,     // memory read enable
+  output [1:0]                          ic2memReqWay_o,
+
   input  [`ICACHE_TAG_BITS-1:0]         mem2icTag_i,          // tag of the incoming data
   input  [`ICACHE_INDEX_BITS-1:0]       mem2icIndex_i,        // index of the incoming data
   input  [`ICACHE_BITS_IN_LINE-1:0]     mem2icData_i,         // requested data
   input                                 mem2icRespValid_i,    // requested data is ready
 
   input                                 mem2icInv_i,          // icache invalidation
   input  [`ICACHE_INDEX_BITS-1:0]       mem2icInvInd_i,       // icache invalidation index
-  input  [0:0]                          mem2icInvWay_i,       // icache invalidation way (unused)
+  input  [1:0]                          mem2icInvWay_i,       // icache invalidation way (unused)
 
   input                                 icScratchModeEn_i,    // Should ideally be disabled by default
   input  [`ICACHE_INDEX_BITS+`ICACHE_BYTES_IN_LINE_LOG-1:0]  icScratchWrAddr_i,
@@ -310,6 +312,7 @@ module L1ICache (
       .icFlushDone_o          (icFlushDone_o),
       .ic2memReqAddr_o        (ic2memReqAddr_o),
       .ic2memReqValid_o       (ic2memReqValid_o),
+      .ic2memReqWay_o         (ic2memReqWay_o),
 
       .icScratchWrAddr_i      (icScratchWrAddr_i),
       .icScratchWrEn_i        (icScratchWrEn_i  ),