0.7.1

What's Changed

• Static Systolic Array by @calebmkim in #1740
• Add width parameter to pipelined_mult primitive by @matth2k in #1748
• Automate SystemVerilog to BTOR conversion for Calyx Primitives by @NgaiJustin in #1757
• Share cells in more situations by @bcarlet in #1753
• Promotion Heurisitcs (subsumes #1750) by @calebmkim in #1758
• Systolic Generation Optimization by @calebmkim in #1760
• fifo: better testing by @anshumanmohan in #1762
• Schedule Compaction Minimizes Par Threads by @calebmkim in #1774
• Static interface by @paili0628 in #1759
• fud stages for HLS place and route by @bcarlet in #1773
• Cider-dap changes by @eliascxstro in #1768
• Converted extension.js to typescript by @kadenlei in #1772
• [Cider 2.0] random grab bag of stuff by @EclecticGriffin in #1778
• pifo: better testing by @anshumanmohan in #1763
• PIFO trees: better testing by @anshumanmohan in #1765
• Queues: collect magic numbers, pass 100 commands by @anshumanmohan in #1771
• Queues: option for no errors by @anshumanmohan in #1779
• PIFO Trees: Telemetry by @anshumanmohan in #1736
• PIFO trees for Piezo: no peeks in command list by @anshumanmohan in #1781
• Add Priya, Anshuman to list of contributors by @anshumanmohan in #1782
• Bug Fix by @calebmkim in #1784
• Piezo, PIFOTree: static option! by @anshumanmohan in #1783
• SDN: remove unnecessary par by @anshumanmohan in #1786
• Piezo PIFO trees: More thoughtful data gen by @anshumanmohan in #1787
• Piezo, PIFO tree: new .data and .expect files by @anshumanmohan in #1788
• Fix some typos and rephrase some axi-gen.md documentation by @nathanielnrn in #1789
• Piezo, PIFO tree: 10000 pushes and pops by @anshumanmohan in #1790
• Simplify logic on static designs by @calebmkim in #1775
• Queues: more if then else by @anshumanmohan in #1791
• Add back the vscode settings by @EclecticGriffin in #1799
• Fix pretty-printing for static invokes (#1795) by @sampsyo in #1800
• Cider changes by @eliascxstro in #1798
• Implemented Single session by @kadenlei in #1797
• Cider debugger logging by @kadenlei in #1802
• Use runt version 0.4.0 by @rachitnigam in #1804
• [Docker] bump rust version number by @EclecticGriffin in #1812
• Initial code and tests for Calyx-to-FIRRTL backend by @ayakayorihiro in #1806
• SDN correctness by @anshumanmohan in #1796
• Queues: unified, nicer runner method by @anshumanmohan in #1816
• [Calyx-FIRRTL backend] Guards and non-primitive Cells by @ayakayorihiro in #1817
• Better parsing and help for pass options by @rachitnigam in #1819
• Add that in guards ports can be literals to docs by @nathanielnrn in #1821
• Add Ayaka to list of contributors by @ayakayorihiro in #1822
• Rename cucapra/calyx to calyxir/calyx by @rachitnigam in #1823
• Build docker image if dockerfile changes by @rachitnigam in #1824
• Register options for cell-share by @rachitnigam in #1826
• Update SA docs and command-line opts by @rachitnigam in #1829
• Make stability check a warning by @rachitnigam in #1830
• Remove tdst by @rachitnigam in #1831
• Promote if branches that don't have else stmts by @calebmkim in #1792
• [Calyx-FIRRTL backend] Primitive Cells by @ayakayorihiro in #1835
• [Calyx-FIRRTL] Primitive cell bug fix by @ayakayorihiro in #1838
• Working Calyx Implementation of AXI Read channels by @nathanielnrn in #1820
• [Calyx-Firrtl] Fix undefined values bug by initializing to zero by @ayakayorihiro in #1841
• Promote AXI-Read implementation to a complete AXI wrapper by @nathanielnrn in #1842
• Compaction Accounts for Continuous Assignments by @calebmkim in #1847
• Document Calyx RTL interface requirements by @nathanielnrn in #1843
• Fix read channel read_data_reg write_en by @nathanielnrn in #1851
• Simplify Calyx AXI wrapper -- xVALID signals and reg invokes by @nathanielnrn in #1846
• Add parens around guard exprs by @rachitnigam in #1858
• Add support for using python builder invoke with integer literals by @nathanielnrn in #1849
• Decouple AXI base_addr and calyx memories' curr_addr in hardcoded AXI implementation by @nathanielnrn in #1854
• Add parentheses around == and != in builder by @nathanielnrn in #1859
• [Docs] tiny addition about github practices by @EclecticGriffin in #1840
• Backend for listing instantiations of primitives by @ayakayorihiro in #1860
• Add calyx-py AXI generator address channels by @nathanielnrn in #1855
• Add calyx-py AXI generator read channel by @nathanielnrn in #1856
• Add calyx-py AXI generator write channel by @nathanielnrn in #1861
• [Cider 2.0] Partial checkpoint by @EclecticGriffin in #1868
• [Cider-dap] Fix cider extension by @EclecticGriffin in #1869
• Dont panic if insufficient parameters provided by @rachitnigam in #1876
• Clean up AXI generator channels by @nathanielnrn in #1867
• Initial fud2 import by @sampsyo in #1877
• Add logging to fud2 by @rachitnigam in #1881
• [fud2] Add subcommand to edit configuration by @rachitnigam in #1882
• [Calyx-FIRRTL] Support for template FIRRTL primitives by @ayakayorihiro in #1864
• Small tweaks to fud2 by @sampsyo in #1879
• Separate Inference and Promotion into Separate Passes by @calebmkim in #1871
• Reorder Compaction by @calebmkim in #1884
• Docs: static keyword by @anshumanmohan in #1872
• Docs: multicomponent tutorial fud command fix by @eys29 in #1891
• Reorganize fud2 directory by @rachitnigam in #1883
• Deploy docs on main by @rachitnigam in #1892
• Update fud2 docs with edit-config command by @rachitnigam in #1893
• Fix tiny typo for fud2 doc by @ayakayorihiro in #1895
• Move numeric_types.py from fud/verilator to calyx-py (another attempt at #1715 ) by @calebmkim in #1719
• Remove versions/ folder by @rachitnigam in #1900
• Reorganize memories in primitives by @rachitnigam in #1901
• [Calyx-FIRRTL] Debugged FIRRTL implementations of primitives by @ayakayorihiro in #1907
• Deprecate @static by @calebmkim in #1897
• Remove @static from docs by @calebmkim in #1911
• [Cider 2.0] Basic Simulation flow by @EclecticGriffin in #1912
• std-bit-slice implementation by @anthonyabeo in #1906
• Add names to fields in ir::Canonical by @rachitnigam in #1920
• Redesign ReadWriteSet by @rachitnigam in #1921
• Merge Compaction and Promotion by @calebmkim in #1914
• bump rust versions to stable by @sgpthomas in #1925
  *...

0.6.1

0.6.1

• Fix checking for large constants (#1743)
• Better static inlining for single cycle if (#1734)
• Implement schedule-compaction pass to optimize inferred static islands (#1722)
• Add std_signext primitive

0.6.0

• BREAKING: Deprecate Cell::find_with_attr in favor of Cell::find_with_unique_attr. The former is error-prone because pass logic might implicitly assume that there is only one port with a particular attribute.
• BREAKING: Redesign the ir::Rewriter interface to take all the rewrite maps when constructing the ir::Rewriter struct.
• Merge the logic of compile-ref pass into compile-invoke so that ref cells can be invoked.
• The guard! macro supports parsing complex guard expressions that use logical connectives and comparison operators.
• The calyx library no longer exposes any methods and should not be depended upon. Instead, the new calyx-backend crate provides the code needed to emit Verilog from Calyx.

0.5.1

• Change the calyx build script to use the CALYX_PRIMITIVES_DIR env variable to install primitive libraries. If unset, use $HOME/.calyx.

0.5.0

• Don't require @clk and @reset ports in comb components
• inline pass supports inlining ref cells
• comb-prop: disable rewrite from wire.in = port when the output of a wire is read.
• BREAKING: Remove PortDef::into() because it makes it easy to miss copying attributes.
• Remove the futil binary.
• The calyx binary ships all the primitives and therefore self-contained now.
  • Add the calyx-stdlib package
  • Add a new build script that installs primitives when the package is installed.

0.4.0

• Language: New repeat operator that can be used in dynamic contexts as well. When possible, static-promotion will attempt to promote it.
• Fix: wrap-main correctly instantiates the original "toplevel" component in the generated main component.
• Make Workspace::construct_with_all_deps public to allow construction of multi-file workspaces.
• Don't emit clk ports for @external cells in the AXI generator.
• BREAKING: Redesign the interface for LibrarySignatures.
  • Expose methods to add new primitives to the library
  • Rewrite the IR printer to print out source primitives when skip_primitive is set.

Version 0.3.0

• ir::Component takes a has_interface argument and ensures that interface ports are present when it is true.
• The Visitor trait supports new start_context and finish_context methods which allow the pass to affect the context before and after the components are visited respectively.
• New wrap-main pass that generates a top-level main component if the top-level component is not named that.
• Pretty printer prints code more tersely.

Version 0.2.1

• Remove necessary indentation inlined verilog primitives
• Add new discover-external pass to transform inlined cells into @external cells
• Implementation of static primitives and components and finish work on static milestone paving way for deprecation of the @static attribute.

ASPLOS 21

State of the repository for the ASPLOS '21 submission