🎨 Improved usability of the on-the-fly SiDB gate library

bindings/mnt/pyfiction/include/pyfiction/algorithms/physical_design/design_sidb_gates.hpp

@@ -47,7 +47,7 @@ inline void design_sidb_gates(pybind11::module& m)
     /**
      * Design approach selector type.
      */
-    pybind11::enum_<typename fiction::design_sidb_gates_params<fiction::offset::ucoord_t>::design_sidb_gates_mode>(
+    py::enum_<typename fiction::design_sidb_gates_params<fiction::offset::ucoord_t>::design_sidb_gates_mode>(
         m, "design_sidb_gates_mode", DOC(fiction_design_sidb_gates_params_design_sidb_gates_mode))
         .value("QUICKCELL",
                fiction::design_sidb_gates_params<fiction::offset::ucoord_t>::design_sidb_gates_mode::QUICKCELL,
@@ -72,9 +72,9 @@ inline void design_sidb_gates(pybind11::module& m)
                        DOC(fiction_design_sidb_gates_params_design_mode))
         .def_readwrite("canvas", &fiction::design_sidb_gates_params<fiction::offset::ucoord_t>::canvas,
                        DOC(fiction_design_sidb_gates_params_canvas))
-        .def_readwrite("number_of_sidbs",
-                       &fiction::design_sidb_gates_params<fiction::offset::ucoord_t>::number_of_sidbs,
-                       DOC(fiction_design_sidb_gates_params_number_of_sidbs));
+        .def_readwrite("number_of_canvas_sidbs",
+                       &fiction::design_sidb_gates_params<fiction::offset::ucoord_t>::number_of_canvas_sidbs,
+                       DOC(fiction_design_sidb_gates_params_number_of_canvas_sidbs));
 
     detail::design_sidb_gates<py_sidb_100_lattice>(m);
     detail::design_sidb_gates<py_sidb_111_lattice>(m);

bindings/mnt/pyfiction/include/pyfiction/algorithms/simulation/sidb/calculate_energy_and_state_type.hpp

@@ -42,7 +42,6 @@ void calculate_energy_and_state_type(pybind11::module& m)
 inline void calculate_energy_and_state_type(pybind11::module& m)
 {
     // NOTE be careful with the order of the following calls! Python will resolve the first matching overload!
-
     detail::calculate_energy_and_state_type<py_sidb_100_lattice>(m);
     detail::calculate_energy_and_state_type<py_sidb_111_lattice>(m);
 }

bindings/mnt/pyfiction/include/pyfiction/algorithms/simulation/sidb/sidb_simulation_result.hpp

@@ -26,7 +26,6 @@ template <typename Lyt>
 void sidb_simulation_result(pybind11::module& m, const std::string& lattice = "")
 {
     namespace py = pybind11;
-    namespace py = pybind11;
 
     py::class_<fiction::sidb_simulation_result<Lyt>>(m, fmt::format("sidb_simulation_result{}", lattice).c_str(),
                                                      DOC(fiction_sidb_simulation_result))

bindings/mnt/pyfiction/include/pyfiction/layouts/cell_level_layout.hpp

@@ -124,6 +124,13 @@ void fcn_technology_cell_level_layout(pybind11::module& m)
         .def("is_pi", &py_cartesian_technology_cell_layout::is_pi, py::arg("c"), DOC(fiction_cell_level_layout_is_pi))
         .def("is_po", &py_cartesian_technology_cell_layout::is_po, py::arg("c"), DOC(fiction_cell_level_layout_is_po))
 
+        .def("get_cell_type", &py_cartesian_technology_cell_layout::get_cell_type, py::arg("c"),
+             DOC(fiction_cell_level_layout_get_cell_type))
+        .def("get_cells_by_type", &py_cartesian_technology_cell_layout::get_cells_by_type, py::arg("type"),
+             DOC(fiction_cell_level_layout_get_cells_by_type))
+        .def("num_cells_of_given_type", &py_cartesian_technology_cell_layout::num_cells_of_given_type, py::arg("type"),
+             DOC(fiction_cell_level_layout_num_cells_of_given_type))
+
         .def("cells",
              [](const py_cartesian_technology_cell_layout& lyt)
              {

bindings/mnt/pyfiction/include/pyfiction/technology/charge_distribution_surface.hpp

@@ -32,7 +32,6 @@ template <typename Lyt>
 void charge_distribution_surface_layout(pybind11::module& m, const std::string& lattice = "")
 {
     namespace py = pybind11;
-    namespace py = pybind11;
 
     using py_cds = py_charge_distribution_surface_layout<Lyt>;
 

bindings/mnt/pyfiction/include/pyfiction/technology/sidb_lattice.hpp

@@ -32,7 +32,6 @@ template <typename LatticeOrientation>
 void sidb_lattice_cell_level_layout(pybind11::module& m)
 {
     namespace py = pybind11;
-    namespace py = pybind11;
 
     // fetch technology name
     auto orientation = std::string{fiction::sidb_lattice_name<LatticeOrientation>};

bindings/mnt/pyfiction/test/algorithms/physical_design/test_design_sidb_gates.py

@@ -40,11 +40,11 @@ def test_siqad_and_gate_skeleton_100(self):
         params.operational_params.simulation_parameters.mu_minus = -0.28
         params.design_mode = design_sidb_gates_mode.AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER
         params.canvas = [(4, 8), (14, 11)]
-        params.number_of_sidbs = 1
+        params.number_of_canvas_sidbs = 1
         params.operational_params.sim_engine = sidb_simulation_engine.QUICKEXACT
 
         self.assertEqual(params.operational_params.simulation_parameters.mu_minus, -0.28)
-        self.assertEqual(params.number_of_sidbs, 1)
+        self.assertEqual(params.number_of_canvas_sidbs, 1)
         self.assertEqual(params.canvas[0], (4, 8, 0))
         self.assertEqual(params.canvas[1], (14, 11))
 
@@ -86,12 +86,12 @@ def test_nor_gate_111(self):
         params.operational_params.simulation_parameters.mu_minus = -0.32
         params.design_mode = design_sidb_gates_mode.AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER
         params.canvas = [(10, 22), (14, 34)]
-        params.number_of_sidbs = 3
+        params.number_of_canvas_sidbs = 3
         params.operational_params.sim_engine = sidb_simulation_engine.QUICKEXACT
         params.operational_params.op_condition = operational_condition.REJECT_KINKS
 
         self.assertEqual(params.operational_params.simulation_parameters.mu_minus, -0.32)
-        self.assertEqual(params.number_of_sidbs, 3)
+        self.assertEqual(params.number_of_canvas_sidbs, 3)
         self.assertEqual(params.canvas[0], (10, 22, 0))
         self.assertEqual(params.canvas[1], (14, 34))
 
@@ -138,11 +138,11 @@ def test_nor_gate_111_quickcell(self):
         params.design_mode = design_sidb_gates_mode.AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER
 
         params.canvas = [(10, 26), (14, 34)]
-        params.number_of_sidbs = 3
+        params.number_of_canvas_sidbs = 3
         params.operational_params.sim_engine = sidb_simulation_engine.QUICKEXACT
 
         self.assertEqual(params.operational_params.simulation_parameters.mu_minus, -0.32)
-        self.assertEqual(params.number_of_sidbs, 3)
+        self.assertEqual(params.number_of_canvas_sidbs, 3)
         self.assertEqual(params.canvas[0], (10, 26, 0))
         self.assertEqual(params.canvas[1], (14, 34))
 

bindings/mnt/pyfiction/test/layouts/test_cell_level_layout.py

@@ -67,6 +67,9 @@ def test_cell_type_assignment(self):
         layout.assign_cell_type((3, 2), qca_technology.cell_type.NORMAL)
         layout.assign_cell_type((4, 2), qca_technology.cell_type.OUTPUT)
 
+        self.assertEqual(layout.get_cells_by_type(qca_technology.cell_type.OUTPUT), [(4, 2)])
+        self.assertEqual(layout.num_cells_of_given_type(qca_technology.cell_type.INPUT), 2)
+
         self.assertFalse(layout.is_empty())
 
         layout.assign_cell_name((0, 2), "a")

docs/algorithms/apply_gate_library.rst

@@ -13,6 +13,7 @@ implementations for each gate present in the passed ``gate_level_layout``.
 
         .. doxygenfunction:: fiction::apply_gate_library(const GateLyt& lyt)
         .. doxygenfunction:: fiction::apply_parameterized_gate_library(const GateLyt& lyt, const Params& params)
+        .. doxygenfunction:: fiction::apply_parameterized_gate_library(const GateLyt& lyt, const Params& params, const std::optional<CellLyt>& cell_lyt = std::nullopt)
 
     .. tab:: Python
         .. autofunction:: mnt.pyfiction.apply_qca_one_library

docs/algorithms/on_the_fly_circuit_design_on_defective_surface.rst

@@ -1,6 +1,6 @@
 .. _on_the_fly_design:
 
-SiDB Circuit Design Algorithm in the Presence of Atomic Defects
+SiDB Circuit Design Algorithm on defectivein the Presence of Atomic Defects
 ---------------------------------------------------------------
 
 This algorithm is designed to create SiDB circuits on a clocked surface, accommodating the presence of atomic defects.
@@ -24,10 +24,13 @@ This algorithm is designed to create SiDB circuits on a clocked surface, accommo
 This iterative approach ensures that the designed SiDB circuits can effectively handle defects present on the surface.
 
 
-**Header:** ``fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp``
+**Header:** ``fiction/algorithms/physical_design/on_the_fly_circuit_design.hpp``
 
-.. doxygenstruct:: fiction::on_the_fly_circuit_design_params
+.. doxygenstruct:: fiction::on_the_fly_sidb_circuit_design_on_defective_surface_params
    :members:
-.. doxygenstruct:: fiction::on_the_fly_circuit_design_stats
+.. doxygenstruct:: fiction::on_the_fly_sidb_circuit_design_params
+   :members:
+.. doxygenstruct:: fiction::on_the_fly_circuit_design_on_defective_surface_stats
     :members:
-.. doxygenfunction:: fiction::on_the_fly_circuit_design_on_defective_surface
+.. doxygenfunction:: fiction::on_the_fly_sidb_circuit_design_on_defective_surface
+.. doxygenfunction:: fiction::on_the_fly_sidb_circuit_design

experiments/operational_domain/operational_domain_bestagon_exact_vs_sketch.cpp

@@ -129,7 +129,8 @@ int main()  // NOLINT
         opdomain_exp.table();
     }
 
-    opdomain_exp("Average", 0, 0, 0.0, 0, 0.0, mean_ratio_num_op_sketch_to_num_op_exact, 0.0);
+    opdomain_exp("Average", 0, 0, 0.0, 0, 0.0, mean_ratio_num_op_sketch_to_num_op_exact / truth_tables_and_names.size(),
+                 0.0);
 
     opdomain_exp.save();
     opdomain_exp.table();

experiments/physical_design_with_on_the_fly_gate_design/physical_design_with_on_the_fly_gate_design.cpp → experiments/physical_design_with_on_the_fly_gate_design/on_the_fly_sidb_circuit_design_on_defective_surface.cpp

@@ -8,12 +8,11 @@
 
 #include <fiction/algorithms/network_transformation/technology_mapping.hpp>
 #include <fiction/algorithms/physical_design/design_sidb_gates.hpp>
-#include <fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp>
+#include <fiction/algorithms/physical_design/on_the_fly_sidb_circuit_design.hpp>
 #include <fiction/algorithms/simulation/sidb/sidb_simulation_engine.hpp>
 #include <fiction/io/read_sidb_surface_defects.hpp>
+#include <fiction/io/write_sqd_layout.hpp>
 #include <fiction/layouts/bounding_box.hpp>
-#include <fiction/technology/area.hpp>
-#include <fiction/technology/cell_technologies.hpp>
 #include <fiction/technology/sidb_defect_surface.hpp>
 #include <fiction/technology/sidb_defects.hpp>
 #include <fiction/traits.hpp>
@@ -53,7 +52,7 @@ int main()  // NOLINT
     // needs to be changed if a different skeleton is used.
     design_gate_params.canvas = {{24, 17}, {34, 28}};
 
-    design_gate_params.number_of_sidbs               = 3;
+    design_gate_params.number_of_canvas_sidbs        = 3;
     design_gate_params.operational_params.sim_engine = fiction::sidb_simulation_engine::QUICKEXACT;
     design_gate_params.termination_cond =
         fiction::design_sidb_gates_params<fiction::cell<cell_lyt>>::termination_condition::AFTER_FIRST_SOLUTION;
@@ -69,7 +68,7 @@ int main()  // NOLINT
 
     // read-in the initial defects. Physical parameters of the defects are not stored yet.
     auto surface_lattice_initial = fiction::read_sidb_surface_defects<cell_lyt>(
-        "../../experiments/physical_design_with_on_the_fly_gate_design/1_percent_with_charged_surface.txt");
+        "../../experiments/physical_design_with_on_the_fly_gate_design/0.5_percent_with_charged_surface.txt");
 
     // create an empty surface.
     fiction::sidb_defect_surface<cell_lyt> surface_lattice{};
@@ -98,8 +97,8 @@ int main()  // NOLINT
 
     const auto lattice_tiling = gate_lyt{{11, 30}};
 
-    experiments::experiment<std::string, double, uint64_t, bool> sidb_circuits_with_defects{
-        "sidb_circuits_with_defects", "benchmark", "runtime", "number of aspect ratios", "equivalent"};
+    experiments::experiment<std::string, double, uint64_t, bool, uint64_t> sidb_circuits_with_defects{
+        "sidb_circuits_with_defects", "benchmark", "runtime", "number of aspect ratios", "equivalent", "#SiDBs"};
 
     constexpr const uint64_t bench_select =
         fiction_experiments::all & ~fiction_experiments::parity & ~fiction_experiments::two_bit_add_maj &
@@ -119,7 +118,7 @@ int main()  // NOLINT
         // compute depth
         const mockturtle::depth_view depth_xag{xag};
 
-        const fiction::technology_mapping_params tech_map_params = fiction::all_2_input_functions();
+        const fiction::technology_mapping_params tech_map_params = fiction::all_standard_2_input_functions();
 
         // parameters for cut rewriting
         mockturtle::cut_rewriting_params cut_params{};
@@ -137,7 +136,8 @@ int main()  // NOLINT
         // perform technology mapping
         const auto mapped_network = fiction::technology_mapping(cut_xag, tech_map_params);
 
-        fiction::on_the_fly_circuit_design_params<cell_lyt> params{};
+        fiction::on_the_fly_sidb_circuit_design_on_defective_surface_params<fiction::cell<cell_lyt>> params{};
+
         params.exact_design_parameters.scheme        = "ROW4";
         params.exact_design_parameters.crossings     = true;
         params.exact_design_parameters.border_io     = false;
@@ -146,35 +146,35 @@ int main()  // NOLINT
         params.exact_design_parameters.upper_bound_y = 30;         // 12 x 31 tiles
         params.exact_design_parameters.timeout       = 3'600'000;  // 1h in ms
 
-        params.sidb_on_the_fly_gate_library_parameters.defect_surface     = surface_lattice;
         params.sidb_on_the_fly_gate_library_parameters.design_gate_params = design_gate_params;
 
-        fiction::on_the_fly_circuit_design_stats<gate_lyt> st{};
-
-        const auto result =
-            fiction::on_the_fly_circuit_design_on_defective_surface<decltype(mapped_network), cell_lyt, gate_lyt>(
-                mapped_network, lattice_tiling, params, &st);
+        fiction::on_the_fly_circuit_design_on_defective_surface_stats<gate_lyt> st{};
 
-        // check equivalence
-        const auto miter = mockturtle::miter<mockturtle::klut_network>(mapped_network, st.gate_layout.value());
-        const auto eq    = mockturtle::equivalence_checking(*miter);
-        assert(eq.has_value());
+        try
+        {
+            const auto result =
+                fiction::on_the_fly_sidb_circuit_design_on_defective_surface<decltype(mapped_network),
+                                                                             decltype(surface_lattice), gate_lyt>(
+                    mapped_network, lattice_tiling, surface_lattice, params, &st);
 
-        // determine bounding box and exclude atomic defects
-        const auto bb = fiction::bounding_box_2d<cell_lyt>(static_cast<cell_lyt>(result));
+            write_sqd_layout(result, fmt::format("{}/{}.sqd", layouts_folder, benchmark));
 
-        // compute area
-        fiction::area_stats                            area_stats{};
-        fiction::area_params<fiction::sidb_technology> area_ps{};
-        fiction::area(bb, area_ps, &area_stats);
+            // check equivalence
+            const auto miter = mockturtle::miter<mockturtle::klut_network>(mapped_network, st.gate_layout.value());
+            const auto eq    = mockturtle::equivalence_checking(*miter);
+            assert(eq.has_value());
 
-        sidb_circuits_with_defects(benchmark, mockturtle::to_seconds(st.time_total), st.exact_stats.num_aspect_ratios,
-                                   *eq);
-        sidb_circuits_with_defects.save();
-        sidb_circuits_with_defects.table();
+            sidb_circuits_with_defects(benchmark, mockturtle::to_seconds(st.time_total),
+                                       st.exact_stats.num_aspect_ratios, *eq, result.num_cells());
 
-        // write a SiQAD simulation file
-        // fiction::write_sqd_layout(result, fmt::format("{}/{}.sqd", layouts_folder, benchmark));
+            sidb_circuits_with_defects.save();
+            sidb_circuits_with_defects.table();
+        }
+        catch (...)
+        {
+            fmt::print("[e] Circuit design was unsuccessful\n");
+            continue;
+        }
     }
 
     return EXIT_SUCCESS;

experiments/quickcell/quickcell_rectangular_gate_library.cpp

@@ -108,15 +108,15 @@ int main()  // NOLINT
         if (gate_name == "cx_2i_top_left_2o_down_right" || gate_name == "ha_2i_top_left_2o_down_right" ||
             gate_name == "hourglass_2i_top_left_2o_down_right")
         {
-            params.number_of_sidbs = num_canvas_sidbs_2_input_2_output;
-            params.canvas          = {{17, 8, 0}, {27, 14, 0}};
+            params.number_of_canvas_sidbs = num_canvas_sidbs_2_input_2_output;
+            params.canvas                 = {{17, 8, 0}, {27, 14, 0}};
             quickcell_design =
                 design_sidb_gates(rectangular_2i_top_left_2o_down_right, truth_table, params, &stats_quickcell);
         }
 
         else
         {
-            params.number_of_sidbs = num_canvas_sidbs;
+            params.number_of_canvas_sidbs = num_canvas_sidbs;
 
             if (gate_name == "fo2_1i_top_2o_left_right")
             {