[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dbg/el2_dbg.sv:27:-`include "el2_param.vh" design/dbg/el2_dbg.sv:28:- )( design/dbg/el2_dbg.sv:29:- // outputs to the core for command and data interface design/dbg/el2_dbg.sv:30:- output logic [31:0] dbg_cmd_addr, design/dbg/el2_dbg.sv:31:- output logic [31:0] dbg_cmd_wrdata, design/dbg/el2_dbg.sv:32:- output logic dbg_cmd_valid, design/dbg/el2_dbg.sv:33:- output logic dbg_cmd_write, // 1: write command, 0: read_command design/dbg/el2_dbg.sv:34:- output logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory design/dbg/el2_dbg.sv:35:- output logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command design/dbg/el2_dbg.sv:36:- output logic dbg_core_rst_l, // core reset from dm design/dbg/el2_dbg.sv:37:- design/dbg/el2_dbg.sv:38:- // inputs back from the core/dec design/dbg/el2_dbg.sv:39:- input logic [31:0] core_dbg_rddata, design/dbg/el2_dbg.sv:40:- input logic core_dbg_cmd_done, // This will be treated like a valid signal design/dbg/el2_dbg.sv:41:- input logic core_dbg_cmd_fail, // Exception during command run design/dbg/el2_dbg.sv:42:- design/dbg/el2_dbg.sv:43:- // Signals to dma to get a bubble design/dbg/el2_dbg.sv:44:- output logic dbg_dma_bubble, // Debug needs a bubble to send a valid design/dbg/el2_dbg.sv:45:- input logic dma_dbg_ready, // DMA is ready to accept debug request design/dbg/el2_dbg.sv:46:- design/dbg/el2_dbg.sv:47:- // interface with the rest of the core to halt/resume handshaking design/dbg/el2_dbg.sv:48:- output logic dbg_halt_req, // This is a pulse design/dbg/el2_dbg.sv:49:- output logic dbg_resume_req, // Debug sends a resume requests. Pulse design/dbg/el2_dbg.sv:50:- input logic dec_tlu_debug_mode, // Core is in debug mode design/dbg/el2_dbg.sv:51:- input logic dec_tlu_dbg_halted, // The core has finished the queiscing sequence. Core is halted now design/dbg/el2_dbg.sv:52:- input logic dec_tlu_mpc_halted_only, // Only halted due to MPC design/dbg/el2_dbg.sv:53:- input logic dec_tlu_resume_ack, // core sends back an ack for the resume (pulse) design/dbg/el2_dbg.sv:54:- design/dbg/el2_dbg.sv:55:- // inputs from the JTAG design/dbg/el2_dbg.sv:56:- input logic dmi_reg_en, // read or write design/dbg/el2_dbg.sv:57:- input logic [6:0] dmi_reg_addr, // address of DM register design/dbg/el2_dbg.sv:58:- input logic dmi_reg_wr_en, // write instruction design/dbg/el2_dbg.sv:59:- input logic [31:0] dmi_reg_wdata, // write data design/dbg/el2_dbg.sv:60:- design/dbg/el2_dbg.sv:61:- // output design/dbg/el2_dbg.sv:62:- output logic [31:0] dmi_reg_rdata, // read data design/dbg/el2_dbg.sv:63:- design/dbg/el2_dbg.sv:64:- // AXI Write Channels design/dbg/el2_dbg.sv:65:- output logic sb_axi_awvalid, design/dbg/el2_dbg.sv:66:- input logic sb_axi_awready, design/dbg/el2_dbg.sv:67:- /* exclude signals that are tied to constant value in this file */ design/dbg/el2_dbg.sv:68:- /*verilator coverage_off*/ design/dbg/el2_dbg.sv:69:- output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, design/dbg/el2_dbg.sv:70:- /*verilator coverage_on*/ design/dbg/el2_dbg.sv:71:- output logic [31:0] sb_axi_awaddr, design/dbg/el2_dbg.sv:72:- output logic [3:0] sb_axi_awregion, design/dbg/el2_dbg.sv:73:- /* exclude signals that are t

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dbg/el2_dbg.sv:508:- dbg_state_en = (dmstatus_reg[9] & resumereq) | execute_command | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only); design/dbg/el2_dbg.sv:509:- abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START)); // write busy when a new command was written by jtag design/dbg/el2_dbg.sv:510:- abstractcs_busy_din = 1'b1; design/dbg/el2_dbg.sv:511:- dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming design/dbg/el2_dbg.sv:512:- end design/dbg/el2_dbg.sv:513:- CORE_CMD_START: begin design/dbg/el2_dbg.sv:514:- // Don't execute the command if cmderror or transfer=0 for abstract register access design/dbg/el2_dbg.sv:515:- dbg_nxtstate = ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CORE_CMD_WAIT; // new command sent to the core design/dbg/el2_dbg.sv:516:- dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]); design/dbg/el2_dbg.sv:517:- end design/dbg/el2_dbg.sv:518:- CORE_CMD_WAIT: begin design/dbg/el2_dbg.sv:519:- dbg_nxtstate = CMD_DONE; design/dbg/el2_dbg.sv:520:- dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command design/dbg/el2_dbg.sv:521:- end design/dbg/el2_dbg.sv:522:- SB_CMD_START: begin design/dbg/el2_dbg.sv:523:- dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : SB_CMD_SEND; design/dbg/el2_dbg.sv:524:- dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]); design/dbg/el2_dbg.sv:525:- end design/dbg/el2_dbg.sv:526:- SB_CMD_SEND: begin design/dbg/el2_dbg.sv:527:- sb_abmem_cmd_done_in = 1'b1; design/dbg/el2_dbg.sv:528:- sb_abmem_data_done_in= 1'b1; design/dbg/el2_dbg.sv:529:- sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:530:- sb_abmem_data_done_en= (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:531:- dbg_nxtstate = SB_CMD_RESP; design/dbg/el2_dbg.sv:532:- dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:533:- end design/dbg/el2_dbg.sv:534:- SB_CMD_RESP: begin design/dbg/el2_dbg.sv:535:- dbg_nxtstate = CMD_DONE; design/dbg/el2_dbg.sv:536:- dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:537:- dbg_sb_bus_error = (sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error & dbg_bus_clk_en; design/dbg/el2_dbg.sv:538:- data0_reg_wren2 = dbg_state_en & ~sb_abmem_cmd_write & ~dbg_sb_bus_error; design/dbg/el2_dbg.sv:539:- end design/dbg/el2_dbg.sv:540:- CMD_DONE: begin design/dbg/el2_dbg.sv:541:- dbg_nxtstate = HALTED; design/dbg/el2_dbg.sv:542:- dbg_state_en = 1'b1; design/dbg/el2_dbg.sv:543:- abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 ) design/dbg/el2_dbg.sv:544:- abstractcs_busy_din = 1'b0; design/dbg/el2_dbg.sv:545:- sb_abmem_cmd_done_in = 1'b0; design/dbg/el2_dbg.sv:546:- sb_abmem_data_done_in= 1'b0; design/dbg/el2_dbg.sv:547:- sb_abmem

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dbg/el2_dbg.sv:620:- sb_nxtstate = SBIDLE; design/dbg/el2_dbg.sv:621:- sb_state_en = 1'b0; design/dbg/el2_dbg.sv:622:- sbcs_sbbusy_wren = 1'b0; design/dbg/el2_dbg.sv:623:- sbcs_sbbusy_din = 1'b0; design/dbg/el2_dbg.sv:624:- sbcs_sberror_wren = 1'b0; design/dbg/el2_dbg.sv:625:- sbcs_sberror_din[2:0] = 3'b0; design/dbg/el2_dbg.sv:626:- sbaddress0_reg_wren1 = 1'b0; design/dbg/el2_dbg.sv:627:- case (sb_state) design/dbg/el2_dbg.sv:628:- SBIDLE: begin design/dbg/el2_dbg.sv:629:- sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD; design/dbg/el2_dbg.sv:630:- sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22]; design/dbg/el2_dbg.sv:631:- sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command design/dbg/el2_dbg.sv:632:- sbcs_sbbusy_din = 1'b1; design/dbg/el2_dbg.sv:633:- sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits design/dbg/el2_dbg.sv:634:- sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; design/dbg/el2_dbg.sv:635:- end design/dbg/el2_dbg.sv:636:- WAIT_RD: begin design/dbg/el2_dbg.sv:637:- sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD; design/dbg/el2_dbg.sv:638:- sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:639:- sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:640:- sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; design/dbg/el2_dbg.sv:641:- end design/dbg/el2_dbg.sv:642:- WAIT_WR: begin design/dbg/el2_dbg.sv:643:- sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR; design/dbg/el2_dbg.sv:644:- sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:645:- sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:646:- sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; design/dbg/el2_dbg.sv:647:- end design/dbg/el2_dbg.sv:648:- CMD_RD : begin design/dbg/el2_dbg.sv:649:- sb_nxtstate = RSP_RD; design/dbg/el2_dbg.sv:650:- sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en; design/dbg/el2_dbg.sv:651:- end design/dbg/el2_dbg.sv:652:- CMD_WR : begin design/dbg/el2_dbg.sv:653:- sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data) ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA); design/dbg/el2_dbg.sv:654:- sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:655:- end design/dbg/el2_dbg.sv:656:- CMD_WR_ADDR : begin design/dbg/el2_dbg.sv:657:- sb_nxtstate = RSP_WR; design/dbg/el2_dbg.sv:658:- sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en; design/dbg/el2_dbg.sv:659:- end design/dbg/el2_dbg.sv:660:- CMD_WR_DATA : begin design/dbg/el2_dbg.sv:661:- sb_nxtstate = RSP_WR; design/dbg/el2_dbg.sv:662:- sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en; design/dbg/el2_dbg.sv:663:- end design/dbg/el2_dbg.sv:664:- RSP_RD: begin design/dbg/el2_dbg.sv:665:- sb_nxtstate

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:49:- //-------------------------- LSU AXI signals-------------------------- design/el2_veer_wrapper.sv:50:- // AXI Write Channels design/el2_veer_wrapper.sv:51:- output logic lsu_axi_awvalid, design/el2_veer_wrapper.sv:52:- input logic lsu_axi_awready, design/el2_veer_wrapper.sv:53:- output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, design/el2_veer_wrapper.sv:54:- output logic [31:0] lsu_axi_awaddr, design/el2_veer_wrapper.sv:55:- output logic [3:0] lsu_axi_awregion, design/el2_veer_wrapper.sv:56:- output logic [7:0] lsu_axi_awlen, design/el2_veer_wrapper.sv:57:- output logic [2:0] lsu_axi_awsize, design/el2_veer_wrapper.sv:58:- output logic [1:0] lsu_axi_awburst, design/el2_veer_wrapper.sv:59:- output logic lsu_axi_awlock, design/el2_veer_wrapper.sv:60:- output logic [3:0] lsu_axi_awcache, design/el2_veer_wrapper.sv:61:- output logic [2:0] lsu_axi_awprot, design/el2_veer_wrapper.sv:62:- output logic [3:0] lsu_axi_awqos, design/el2_veer_wrapper.sv:63:- design/el2_veer_wrapper.sv:64:- output logic lsu_axi_wvalid, design/el2_veer_wrapper.sv:65:- input logic lsu_axi_wready, design/el2_veer_wrapper.sv:66:- output logic [63:0] lsu_axi_wdata, design/el2_veer_wrapper.sv:67:- output logic [7:0] lsu_axi_wstrb, design/el2_veer_wrapper.sv:68:- output logic lsu_axi_wlast, design/el2_veer_wrapper.sv:69:- design/el2_veer_wrapper.sv:70:- input logic lsu_axi_bvalid, design/el2_veer_wrapper.sv:71:- output logic lsu_axi_bready, design/el2_veer_wrapper.sv:72:- input logic [1:0] lsu_axi_bresp, design/el2_veer_wrapper.sv:73:- input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, design/el2_veer_wrapper.sv:74:- design/el2_veer_wrapper.sv:75:- // AXI Read Channels design/el2_veer_wrapper.sv:76:- output logic lsu_axi_arvalid, design/el2_veer_wrapper.sv:77:- input logic lsu_axi_arready, design/el2_veer_wrapper.sv:78:- output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, design/el2_veer_wrapper.sv:79:- output logic [31:0] lsu_axi_araddr, design/el2_veer_wrapper.sv:80:- output logic [3:0] lsu_axi_arregion, design/el2_veer_wrapper.sv:81:- output logic [7:0] lsu_axi_arlen, design/el2_veer_wrapper.sv:82:- output logic [2:0] lsu_axi_arsize, design/el2_veer_wrapper.sv:83:- output logic [1:0] lsu_axi_arburst, design/el2_veer_wrapper.sv:84:- output logic lsu_axi_arlock, design/el2_veer_wrapper.sv:85:- output logic [3:0] lsu_axi_arcache, design/el2_veer_wrapper.sv:86:- output logic [2:0] lsu_axi_arprot, design/el2_veer_wrapper.sv:87:- output logic [3:0] lsu_axi_arqos, design/el2_veer_wrapper.sv:88:- design/el2_veer_wrapper.sv:89:- input logic lsu_axi_rvalid, design/el2_veer_wrapper.sv:90:- output logic lsu_axi_rready, design/el2_veer_wrapper.sv:91:- input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, design/el2_veer_wrapper.sv:92:- input logic [63:0] lsu_axi_rdata, design/el2_veer_wrapper.sv:93:- input logic [1:0] lsu_axi_rresp, design/el2_veer_wrapper.sv:94:- input logic lsu_axi_rlast, design/el2_veer_wrapper.sv:95:- design/el2_veer_wrapper.sv:96:- //-------------------------- IFU AXI signals-------------------------- design/el2_veer_wrapper.sv:97:- // AXI Write Cha

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:530:- wire lsu_axi_awvalid; design/el2_veer_wrapper.sv:531:- wire lsu_axi_awready; design/el2_veer_wrapper.sv:532:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; design/el2_veer_wrapper.sv:533:- wire [31:0] lsu_axi_awaddr; design/el2_veer_wrapper.sv:534:- wire [3:0] lsu_axi_awregion; design/el2_veer_wrapper.sv:535:- wire [7:0] lsu_axi_awlen; design/el2_veer_wrapper.sv:536:- wire [2:0] lsu_axi_awsize; design/el2_veer_wrapper.sv:537:- wire [1:0] lsu_axi_awburst; design/el2_veer_wrapper.sv:538:- wire lsu_axi_awlock; design/el2_veer_wrapper.sv:539:- wire [3:0] lsu_axi_awcache; design/el2_veer_wrapper.sv:540:- wire [2:0] lsu_axi_awprot; design/el2_veer_wrapper.sv:541:- wire [3:0] lsu_axi_awqos; design/el2_veer_wrapper.sv:542:- design/el2_veer_wrapper.sv:543:- design/el2_veer_wrapper.sv:544:- wire lsu_axi_wvalid; design/el2_veer_wrapper.sv:545:- wire lsu_axi_wready; design/el2_veer_wrapper.sv:546:- wire [63:0] lsu_axi_wdata; design/el2_veer_wrapper.sv:547:- wire [7:0] lsu_axi_wstrb; design/el2_veer_wrapper.sv:548:- wire lsu_axi_wlast; design/el2_veer_wrapper.sv:549:- design/el2_veer_wrapper.sv:550:- wire lsu_axi_bvalid; design/el2_veer_wrapper.sv:551:- wire lsu_axi_bready; design/el2_veer_wrapper.sv:552:- wire [1:0] lsu_axi_bresp; design/el2_veer_wrapper.sv:553:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid; design/el2_veer_wrapper.sv:554:- design/el2_veer_wrapper.sv:555:- // AXI Read Channels design/el2_veer_wrapper.sv:556:- wire lsu_axi_arvalid; design/el2_veer_wrapper.sv:557:- wire lsu_axi_arready; design/el2_veer_wrapper.sv:558:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid; design/el2_veer_wrapper.sv:559:- wire [31:0] lsu_axi_araddr; design/el2_veer_wrapper.sv:560:- wire [3:0] lsu_axi_arregion; design/el2_veer_wrapper.sv:561:- wire [7:0] lsu_axi_arlen; design/el2_veer_wrapper.sv:562:- wire [2:0] lsu_axi_arsize; design/el2_veer_wrapper.sv:563:- wire [1:0] lsu_axi_arburst; design/el2_veer_wrapper.sv:564:- wire lsu_axi_arlock; design/el2_veer_wrapper.sv:565:- wire [3:0] lsu_axi_arcache; design/el2_veer_wrapper.sv:566:- wire [2:0] lsu_axi_arprot; design/el2_veer_wrapper.sv:567:- wire [3:0] lsu_axi_arqos; design/el2_veer_wrapper.sv:568:- design/el2_veer_wrapper.sv:569:- wire lsu_axi_rvalid; design/el2_veer_wrapper.sv:570:- wire lsu_axi_rready; design/el2_veer_wrapper.sv:571:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid; design/el2_veer_wrapper.sv:572:- wire [63:0] lsu_axi_rdata; design/el2_veer_wrapper.sv:573:- wire [1:0] lsu_axi_rresp; design/el2_veer_wrapper.sv:574:- wire lsu_axi_rlast; design/el2_veer_wrapper.sv:575:- design/el2_veer_wrapper.sv:576:- assign lsu_axi_awready = '0; design/el2_veer_wrapper.sv:577:- assign lsu_axi_wready = '0; design/el2_veer_wrapper.sv:578:- assign lsu_axi_bvalid = '0; design/el2_veer_wrapper.sv:579:- assign lsu_axi_bresp = '0; design/el2_veer_wrapper.sv:580:- assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}}; design/el2_veer_wrapper.sv:581:- assign lsu_axi_arready = '0; desi

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:27:-`include "el2_param.vh" design/ifu/el2_ifu_mem_ctl.sv:28:- ) design/ifu/el2_ifu_mem_ctl.sv:29:- ( design/ifu/el2_ifu_mem_ctl.sv:30:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu_mem_ctl.sv:31:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu_mem_ctl.sv:32:- input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. design/ifu/el2_ifu_mem_ctl.sv:33:- input logic rst_l, // reset, active low design/ifu/el2_ifu_mem_ctl.sv:34:- design/ifu/el2_ifu_mem_ctl.sv:35:- input logic exu_flush_final, // Flush from the pipeline., includes flush lower design/ifu/el2_ifu_mem_ctl.sv:36:- input logic dec_tlu_flush_lower_wb, // Flush lower from the pipeline. design/ifu/el2_ifu_mem_ctl.sv:37:- input logic dec_tlu_flush_err_wb, // Flush from the pipeline due to perr. design/ifu/el2_ifu_mem_ctl.sv:38:- input logic dec_tlu_i0_commit_cmt, // committed i0 instruction design/ifu/el2_ifu_mem_ctl.sv:39:- input logic dec_tlu_force_halt, // force halt. design/ifu/el2_ifu_mem_ctl.sv:40:- design/ifu/el2_ifu_mem_ctl.sv:41:- input logic [31:1] ifc_fetch_addr_bf, // Fetch Address byte aligned always. F1 stage. design/ifu/el2_ifu_mem_ctl.sv:42:- input logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. F1 stage design/ifu/el2_ifu_mem_ctl.sv:43:- input logic ifc_fetch_req_bf, // Fetch request. Comes with the address. F1 stage design/ifu/el2_ifu_mem_ctl.sv:44:- input logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. F1 stage design/ifu/el2_ifu_mem_ctl.sv:45:- input logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus. design/ifu/el2_ifu_mem_ctl.sv:46:- input logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM. design/ifu/el2_ifu_mem_ctl.sv:47:- input logic ifc_dma_access_ok, // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle). design/ifu/el2_ifu_mem_ctl.sv:48:- input logic dec_tlu_fence_i_wb, // Fence.i instruction is committing. Clear all Icache valids. design/ifu/el2_ifu_mem_ctl.sv:49:- input logic ifu_bp_hit_taken_f, // Branch is predicted taken. Kill the fetch next cycle. design/ifu/el2_ifu_mem_ctl.sv:50:- design/ifu/el2_ifu_mem_ctl.sv:51:- input logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified design/ifu/el2_ifu_mem_ctl.sv:52:- design/ifu/el2_ifu_mem_ctl.sv:53:- output logic ifu_miss_state_idle, // No icache misses are outstanding. design/ifu/el2_ifu_mem_ctl.sv:54:- output logic ifu_ic_mb_empty, // Continue with normal fetching. This does not mean that miss is finished. design/ifu/el2_ifu_mem_ctl.sv:55:- output logic ic_dma_active , // In the middle of servicing dma request to ICCM. Do not make any new requests. design/ifu/el2_ifu_mem_ctl.sv:56:- output logic ic_write_stall, // Stall fetch the cycle we are writing th

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/lsu/el2_lsu_bus_buffer.sv:29:-`include "el2_param.vh" design/lsu/el2_lsu_bus_buffer.sv:30:- )( design/lsu/el2_lsu_bus_buffer.sv:31:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/lsu/el2_lsu_bus_buffer.sv:32:- input logic clk_override, // Override non-functional clock gating design/lsu/el2_lsu_bus_buffer.sv:33:- input logic rst_l, // reset, active low design/lsu/el2_lsu_bus_buffer.sv:34:- input logic scan_mode, // scan mode design/lsu/el2_lsu_bus_buffer.sv:35:- input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals design/lsu/el2_lsu_bus_buffer.sv:36:- input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing design/lsu/el2_lsu_bus_buffer.sv:37:- input logic dec_tlu_sideeffect_posted_disable, // Don't block the sideeffect load store to the bus design/lsu/el2_lsu_bus_buffer.sv:38:- input logic dec_tlu_force_halt, design/lsu/el2_lsu_bus_buffer.sv:39:- design/lsu/el2_lsu_bus_buffer.sv:40:- // various clocks needed for the bus reads and writes design/lsu/el2_lsu_bus_buffer.sv:41:- input logic lsu_bus_obuf_c1_clken, design/lsu/el2_lsu_bus_buffer.sv:42:- input logic lsu_busm_clken, design/lsu/el2_lsu_bus_buffer.sv:43:- input logic lsu_c2_r_clk, design/lsu/el2_lsu_bus_buffer.sv:44:- input logic lsu_bus_ibuf_c1_clk, design/lsu/el2_lsu_bus_buffer.sv:45:- input logic lsu_bus_obuf_c1_clk, design/lsu/el2_lsu_bus_buffer.sv:46:- input logic lsu_bus_buf_c1_clk, design/lsu/el2_lsu_bus_buffer.sv:47:- input logic lsu_free_c2_clk, design/lsu/el2_lsu_bus_buffer.sv:48:- input logic lsu_busm_clk, design/lsu/el2_lsu_bus_buffer.sv:49:- design/lsu/el2_lsu_bus_buffer.sv:50:- design/lsu/el2_lsu_bus_buffer.sv:51:- input logic dec_lsu_valid_raw_d, // Raw valid for address computation design/lsu/el2_lsu_bus_buffer.sv:52:- input el2_lsu_pkt_t lsu_pkt_m, // lsu packet flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:53:- input el2_lsu_pkt_t lsu_pkt_r, // lsu packet flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:54:- design/lsu/el2_lsu_bus_buffer.sv:55:- input logic [31:0] lsu_addr_m, // lsu address flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:56:- input logic [31:0] end_addr_m, // lsu address flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:57:- input logic [31:0] lsu_addr_r, // lsu address flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:58:- input logic [31:0] end_addr_r, // lsu address flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:59:- input logic [31:0] store_data_r, // store data flowing down the pipe design/lsu/el2_lsu_bus_buffer.sv:60:- design/lsu/el2_lsu_bus_buffer.sv:61:- input logic no_word_merge_r, // r store doesn't need to wait in ibuf since it will not coalesce design/lsu/el2_lsu_bus_buffer.sv:62:- input logic no_dword_merge_r, // r store doesn't need to wait in ibuf since it will not coalesce design/lsu/el2_lsu_bus_buffer.sv:63:- input logic lsu_busreq_m, // bus request is in m de