[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dbg/el2_dbg.sv:27:-`include "el2_param.vh" design/dbg/el2_dbg.sv:28:- )( design/dbg/el2_dbg.sv:29:- // outputs to the core for command and data interface design/dbg/el2_dbg.sv:30:- output logic [31:0] dbg_cmd_addr, design/dbg/el2_dbg.sv:31:- output logic [31:0] dbg_cmd_wrdata, design/dbg/el2_dbg.sv:32:- output logic dbg_cmd_valid, design/dbg/el2_dbg.sv:33:- output logic dbg_cmd_write, // 1: write command, 0: read_command design/dbg/el2_dbg.sv:34:- output logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory design/dbg/el2_dbg.sv:35:- output logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command design/dbg/el2_dbg.sv:36:- output logic dbg_core_rst_l, // core reset from dm design/dbg/el2_dbg.sv:37:- design/dbg/el2_dbg.sv:38:- // inputs back from the core/dec design/dbg/el2_dbg.sv:39:- input logic [31:0] core_dbg_rddata, design/dbg/el2_dbg.sv:40:- input logic core_dbg_cmd_done, // This will be treated like a valid signal design/dbg/el2_dbg.sv:41:- input logic core_dbg_cmd_fail, // Exception during command run design/dbg/el2_dbg.sv:42:- design/dbg/el2_dbg.sv:43:- // Signals to dma to get a bubble design/dbg/el2_dbg.sv:44:- output logic dbg_dma_bubble, // Debug needs a bubble to send a valid design/dbg/el2_dbg.sv:45:- input logic dma_dbg_ready, // DMA is ready to accept debug request design/dbg/el2_dbg.sv:46:- design/dbg/el2_dbg.sv:47:- // interface with the rest of the core to halt/resume handshaking design/dbg/el2_dbg.sv:48:- output logic dbg_halt_req, // This is a pulse design/dbg/el2_dbg.sv:49:- output logic dbg_resume_req, // Debug sends a resume requests. Pulse design/dbg/el2_dbg.sv:50:- input logic dec_tlu_debug_mode, // Core is in debug mode design/dbg/el2_dbg.sv:51:- input logic dec_tlu_dbg_halted, // The core has finished the queiscing sequence. Core is halted now design/dbg/el2_dbg.sv:52:- input logic dec_tlu_mpc_halted_only, // Only halted due to MPC design/dbg/el2_dbg.sv:53:- input logic dec_tlu_resume_ack, // core sends back an ack for the resume (pulse) design/dbg/el2_dbg.sv:54:- design/dbg/el2_dbg.sv:55:- // inputs from the JTAG design/dbg/el2_dbg.sv:56:- input logic dmi_reg_en, // read or write design/dbg/el2_dbg.sv:57:- input logic [6:0] dmi_reg_addr, // address of DM register design/dbg/el2_dbg.sv:58:- input logic dmi_reg_wr_en, // write instruction design/dbg/el2_dbg.sv:59:- input logic [31:0] dmi_reg_wdata, // write data design/dbg/el2_dbg.sv:60:- design/dbg/el2_dbg.sv:61:- // output design/dbg/el2_dbg.sv:62:- output logic [31:0] dmi_reg_rdata, // read data design/dbg/el2_dbg.sv:63:- design/dbg/el2_dbg.sv:64:- // AXI Write Channels design/dbg/el2_dbg.sv:65:- output logic sb_axi_awvalid, design/dbg/el2_dbg.sv:66:- input logic sb_axi_awready, design/dbg/el2_dbg.sv:67:- /* exclude signals that are tied to constant value in this file */ design/dbg/el2_dbg.sv:68:- /*verilator coverage_off*/ design/dbg/el2_dbg.sv:69:- output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, design/dbg/el2_dbg.sv:70:- /*verilator coverage_on*/ design/dbg/el2_dbg.sv:71:- output logic [31:0] sb_axi_awaddr, design/dbg/el2_dbg.sv:72:- output logic [3:0] sb_axi_awregion, design/dbg/el2_dbg.sv:73:- /* exclude signals that are t

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dbg/el2_dbg.sv:508:- dbg_state_en = (dmstatus_reg[9] & resumereq) | execute_command | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only); design/dbg/el2_dbg.sv:509:- abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START)); // write busy when a new command was written by jtag design/dbg/el2_dbg.sv:510:- abstractcs_busy_din = 1'b1; design/dbg/el2_dbg.sv:511:- dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming design/dbg/el2_dbg.sv:512:- end design/dbg/el2_dbg.sv:513:- CORE_CMD_START: begin design/dbg/el2_dbg.sv:514:- // Don't execute the command if cmderror or transfer=0 for abstract register access design/dbg/el2_dbg.sv:515:- dbg_nxtstate = ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CORE_CMD_WAIT; // new command sent to the core design/dbg/el2_dbg.sv:516:- dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]); design/dbg/el2_dbg.sv:517:- end design/dbg/el2_dbg.sv:518:- CORE_CMD_WAIT: begin design/dbg/el2_dbg.sv:519:- dbg_nxtstate = CMD_DONE; design/dbg/el2_dbg.sv:520:- dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command design/dbg/el2_dbg.sv:521:- end design/dbg/el2_dbg.sv:522:- SB_CMD_START: begin design/dbg/el2_dbg.sv:523:- dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : SB_CMD_SEND; design/dbg/el2_dbg.sv:524:- dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]); design/dbg/el2_dbg.sv:525:- end design/dbg/el2_dbg.sv:526:- SB_CMD_SEND: begin design/dbg/el2_dbg.sv:527:- sb_abmem_cmd_done_in = 1'b1; design/dbg/el2_dbg.sv:528:- sb_abmem_data_done_in= 1'b1; design/dbg/el2_dbg.sv:529:- sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:530:- sb_abmem_data_done_en= (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:531:- dbg_nxtstate = SB_CMD_RESP; design/dbg/el2_dbg.sv:532:- dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:533:- end design/dbg/el2_dbg.sv:534:- SB_CMD_RESP: begin design/dbg/el2_dbg.sv:535:- dbg_nxtstate = CMD_DONE; design/dbg/el2_dbg.sv:536:- dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:537:- dbg_sb_bus_error = (sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error & dbg_bus_clk_en; design/dbg/el2_dbg.sv:538:- data0_reg_wren2 = dbg_state_en & ~sb_abmem_cmd_write & ~dbg_sb_bus_error; design/dbg/el2_dbg.sv:539:- end design/dbg/el2_dbg.sv:540:- CMD_DONE: begin design/dbg/el2_dbg.sv:541:- dbg_nxtstate = HALTED; design/dbg/el2_dbg.sv:542:- dbg_state_en = 1'b1; design/dbg/el2_dbg.sv:543:- abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 ) design/dbg/el2_dbg.sv:544:- abstractcs_busy_din = 1'b0; design/dbg/el2_dbg.sv:545:- sb_abmem_cmd_done_in = 1'b0; design/dbg/el2_dbg.sv:546:- sb_abmem_data_done_in= 1'b0; design/dbg/el2_dbg.sv:547:- sb_abmem

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dbg/el2_dbg.sv:620:- sb_nxtstate = SBIDLE; design/dbg/el2_dbg.sv:621:- sb_state_en = 1'b0; design/dbg/el2_dbg.sv:622:- sbcs_sbbusy_wren = 1'b0; design/dbg/el2_dbg.sv:623:- sbcs_sbbusy_din = 1'b0; design/dbg/el2_dbg.sv:624:- sbcs_sberror_wren = 1'b0; design/dbg/el2_dbg.sv:625:- sbcs_sberror_din[2:0] = 3'b0; design/dbg/el2_dbg.sv:626:- sbaddress0_reg_wren1 = 1'b0; design/dbg/el2_dbg.sv:627:- case (sb_state) design/dbg/el2_dbg.sv:628:- SBIDLE: begin design/dbg/el2_dbg.sv:629:- sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD; design/dbg/el2_dbg.sv:630:- sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22]; design/dbg/el2_dbg.sv:631:- sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command design/dbg/el2_dbg.sv:632:- sbcs_sbbusy_din = 1'b1; design/dbg/el2_dbg.sv:633:- sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits design/dbg/el2_dbg.sv:634:- sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; design/dbg/el2_dbg.sv:635:- end design/dbg/el2_dbg.sv:636:- WAIT_RD: begin design/dbg/el2_dbg.sv:637:- sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD; design/dbg/el2_dbg.sv:638:- sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:639:- sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:640:- sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; design/dbg/el2_dbg.sv:641:- end design/dbg/el2_dbg.sv:642:- WAIT_WR: begin design/dbg/el2_dbg.sv:643:- sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR; design/dbg/el2_dbg.sv:644:- sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:645:- sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; design/dbg/el2_dbg.sv:646:- sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; design/dbg/el2_dbg.sv:647:- end design/dbg/el2_dbg.sv:648:- CMD_RD : begin design/dbg/el2_dbg.sv:649:- sb_nxtstate = RSP_RD; design/dbg/el2_dbg.sv:650:- sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en; design/dbg/el2_dbg.sv:651:- end design/dbg/el2_dbg.sv:652:- CMD_WR : begin design/dbg/el2_dbg.sv:653:- sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data) ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA); design/dbg/el2_dbg.sv:654:- sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en; design/dbg/el2_dbg.sv:655:- end design/dbg/el2_dbg.sv:656:- CMD_WR_ADDR : begin design/dbg/el2_dbg.sv:657:- sb_nxtstate = RSP_WR; design/dbg/el2_dbg.sv:658:- sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en; design/dbg/el2_dbg.sv:659:- end design/dbg/el2_dbg.sv:660:- CMD_WR_DATA : begin design/dbg/el2_dbg.sv:661:- sb_nxtstate = RSP_WR; design/dbg/el2_dbg.sv:662:- sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en; design/dbg/el2_dbg.sv:663:- end design/dbg/el2_dbg.sv:664:- RSP_RD: begin design/dbg/el2_dbg.sv:665:- sb_nxtstate

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:26:-`include "el2_param.vh" design/el2_veer.sv:27:- ) design/el2_veer.sv:28:- ( design/el2_veer.sv:29:- input logic clk, design/el2_veer.sv:30:- input logic rst_l, design/el2_veer.sv:31:- input logic dbg_rst_l, design/el2_veer.sv:32:- input logic [31:1] rst_vec, design/el2_veer.sv:33:- input logic nmi_int, design/el2_veer.sv:34:- input logic [31:1] nmi_vec, design/el2_veer.sv:35:- output logic core_rst_l, // This is "rst_l | dbg_rst_l" design/el2_veer.sv:36:- design/el2_veer.sv:37:- output logic active_l2clk, design/el2_veer.sv:38:- output logic free_l2clk, design/el2_veer.sv:39:- design/el2_veer.sv:40:- output logic [31:0] trace_rv_i_insn_ip, design/el2_veer.sv:41:- output logic [31:0] trace_rv_i_address_ip, design/el2_veer.sv:42:- output logic trace_rv_i_valid_ip, design/el2_veer.sv:43:- output logic trace_rv_i_exception_ip, design/el2_veer.sv:44:- output logic [4:0] trace_rv_i_ecause_ip, design/el2_veer.sv:45:- output logic trace_rv_i_interrupt_ip, design/el2_veer.sv:46:- output logic [31:0] trace_rv_i_tval_ip, design/el2_veer.sv:47:- design/el2_veer.sv:48:- design/el2_veer.sv:49:- output logic dccm_clk_override, design/el2_veer.sv:50:- output logic icm_clk_override, design/el2_veer.sv:51:- output logic dec_tlu_core_ecc_disable, design/el2_veer.sv:52:- design/el2_veer.sv:53:- // external halt/run interface design/el2_veer.sv:54:- input logic i_cpu_halt_req, // Asynchronous Halt request to CPU design/el2_veer.sv:55:- input logic i_cpu_run_req, // Asynchronous Restart request to CPU design/el2_veer.sv:56:- output logic o_cpu_halt_ack, // Core Acknowledge to Halt request design/el2_veer.sv:57:- output logic o_cpu_halt_status, // 1'b1 indicates processor is halted design/el2_veer.sv:58:- output logic o_cpu_run_ack, // Core Acknowledge to run request design/el2_veer.sv:59:- output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request design/el2_veer.sv:60:- design/el2_veer.sv:61:- input logic [31:4] core_id, // CORE ID design/el2_veer.sv:62:- design/el2_veer.sv:63:- // external MPC halt/run interface design/el2_veer.sv:64:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer.sv:65:- input logic mpc_debug_run_req, // Async run request design/el2_veer.sv:66:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer.sv:67:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer.sv:68:- output logic mpc_debug_run_ack, // Run ack design/el2_veer.sv:69:- output logic debug_brkpt_status, // debug breakpoint design/el2_veer.sv:70:- design/el2_veer.sv:71:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer.sv:72:- output logic dec_tlu_perfcnt1, design/el2_veer.sv:73:- output logic dec_tlu_perfcnt2, design/el2_veer.sv:74:- output logic dec_tlu_perfcnt3, design/el2_veer.sv:75:- design/el2_veer.sv:76:- // DCCM ports design/el2_veer.sv:77:- output logic dccm_wren, design/el2_veer.sv:78:- output logic dccm_rden, design/el2_veer.sv:79:- output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, design/el2_veer.sv:80:- output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, design/el2_veer.sv:81:- output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, design/el2_veer.sv:82:- output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, design/el2_veer.sv:83:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, design/el2_veer.sv:84:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, design/el2_veer.sv:85:- design/el2_veer.sv:86:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, design/el2_veer.sv

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:467:- logic [63:0] hwdata_nc; design/el2_veer.sv:468:- //---------------------------------------------------------------------- design/el2_veer.sv:469:- // design/el2_veer.sv:470:- //---------------------------------------------------------------------- design/el2_veer.sv:471:- design/el2_veer.sv:472:- logic ifu_pmu_instr_aligned; design/el2_veer.sv:473:- logic ifu_ic_error_start; design/el2_veer.sv:474:- logic ifu_iccm_dma_rd_ecc_single_err; design/el2_veer.sv:475:- logic ifu_iccm_rd_ecc_single_err; design/el2_veer.sv:476:- logic ifu_iccm_rd_ecc_double_err; design/el2_veer.sv:477:- logic lsu_dccm_rd_ecc_single_err; design/el2_veer.sv:478:- logic lsu_dccm_rd_ecc_double_err; design/el2_veer.sv:479:- design/el2_veer.sv:480:- logic lsu_axi_awready_ahb; design/el2_veer.sv:481:- logic lsu_axi_wready_ahb; design/el2_veer.sv:482:- logic lsu_axi_bvalid_ahb; design/el2_veer.sv:483:- logic lsu_axi_bready_ahb; design/el2_veer.sv:484:- logic [1:0] lsu_axi_bresp_ahb; design/el2_veer.sv:485:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_ahb; design/el2_veer.sv:486:- logic lsu_axi_arready_ahb; design/el2_veer.sv:487:- logic lsu_axi_rvalid_ahb; design/el2_veer.sv:488:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_ahb; design/el2_veer.sv:489:- logic [63:0] lsu_axi_rdata_ahb; design/el2_veer.sv:490:- logic [1:0] lsu_axi_rresp_ahb; design/el2_veer.sv:491:- logic lsu_axi_rlast_ahb; design/el2_veer.sv:492:- design/el2_veer.sv:493:- logic lsu_axi_awready_int; design/el2_veer.sv:494:- logic lsu_axi_wready_int; design/el2_veer.sv:495:- logic lsu_axi_bvalid_int; design/el2_veer.sv:496:- logic lsu_axi_bready_int; design/el2_veer.sv:497:- logic [1:0] lsu_axi_bresp_int; design/el2_veer.sv:498:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int; design/el2_veer.sv:499:- logic lsu_axi_arready_int; design/el2_veer.sv:500:- logic lsu_axi_rvalid_int; design/el2_veer.sv:501:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_int; design/el2_veer.sv:502:- logic [63:0] lsu_axi_rdata_int; design/el2_veer.sv:503:- logic [1:0] lsu_axi_rresp_int; design/el2_veer.sv:504:- logic lsu_axi_rlast_int; design/el2_veer.sv:505:- design/el2_veer.sv:506:- logic ifu_axi_awready_ahb; design/el2_veer.sv:507:- logic ifu_axi_wready_ahb; design/el2_veer.sv:508:- logic ifu_axi_bvalid_ahb; design/el2_veer.sv:509:- logic ifu_axi_bready_ahb; design/el2_veer.sv:510:- logic [1:0] ifu_axi_bresp_ahb; design/el2_veer.sv:511:- logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_ahb; design/el2_veer.sv:512:- logic ifu_axi_arready_ahb; design/el2_veer.sv:513:- logic ifu_axi_rvalid_ahb; design/el2_veer.sv:514:- logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_ahb; design/el2_veer.sv:515:- logic [63:0] ifu_axi_rdata_ahb; design/el2_veer.sv:516:- logic [1:0] ifu_axi_rresp_ahb; design/el2_veer.sv:517:- logic ifu_axi_rlast_ahb; design/el2_veer.sv:518:- design/el2_veer.sv:519:- logic ifu_axi_awready_int; design/el2_veer.sv:520:- logic ifu_axi_wready_int; design/el2_veer.sv:521:- logic ifu_axi_bvalid_int; design/el2_veer.sv:522:- logic

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:49:- //-------------------------- LSU AXI signals-------------------------- design/el2_veer_wrapper.sv:50:- // AXI Write Channels design/el2_veer_wrapper.sv:51:- output logic lsu_axi_awvalid, design/el2_veer_wrapper.sv:52:- input logic lsu_axi_awready, design/el2_veer_wrapper.sv:53:- output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, design/el2_veer_wrapper.sv:54:- output logic [31:0] lsu_axi_awaddr, design/el2_veer_wrapper.sv:55:- output logic [3:0] lsu_axi_awregion, design/el2_veer_wrapper.sv:56:- /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ design/el2_veer_wrapper.sv:57:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:58:- output logic [7:0] lsu_axi_awlen, design/el2_veer_wrapper.sv:59:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:60:- output logic [2:0] lsu_axi_awsize, design/el2_veer_wrapper.sv:61:- /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ design/el2_veer_wrapper.sv:62:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:63:- output logic [1:0] lsu_axi_awburst, design/el2_veer_wrapper.sv:64:- output logic lsu_axi_awlock, design/el2_veer_wrapper.sv:65:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:66:- output logic [3:0] lsu_axi_awcache, design/el2_veer_wrapper.sv:67:- /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ design/el2_veer_wrapper.sv:68:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:69:- output logic [2:0] lsu_axi_awprot, design/el2_veer_wrapper.sv:70:- output logic [3:0] lsu_axi_awqos, design/el2_veer_wrapper.sv:71:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:72:- design/el2_veer_wrapper.sv:73:- output logic lsu_axi_wvalid, design/el2_veer_wrapper.sv:74:- input logic lsu_axi_wready, design/el2_veer_wrapper.sv:75:- output logic [63:0] lsu_axi_wdata, design/el2_veer_wrapper.sv:76:- output logic [7:0] lsu_axi_wstrb, design/el2_veer_wrapper.sv:77:- output logic lsu_axi_wlast, design/el2_veer_wrapper.sv:78:- design/el2_veer_wrapper.sv:79:- input logic lsu_axi_bvalid, design/el2_veer_wrapper.sv:80:- /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ design/el2_veer_wrapper.sv:81:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:82:- output logic lsu_axi_bready, design/el2_veer_wrapper.sv:83:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:84:- input logic [1:0] lsu_axi_bresp, design/el2_veer_wrapper.sv:85:- input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, design/el2_veer_wrapper.sv:86:- design/el2_veer_wrapper.sv:87:- // AXI Read Channels design/el2_veer_wrapper.sv:88:- output logic lsu_axi_arvalid, design/el2_veer_wrapper.sv:89:- input logic lsu_axi_arready, design/el2_veer_wrapper.sv:90:- output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, design/el2_veer_wrapper.sv:91:- output logic [31:0] lsu_axi_araddr, design/el2_veer_wrapper.sv:92:- output logic [3:0] lsu_axi_arregion, design/el2_veer_wrapper.sv:93:- /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ design/el2_veer_wrapper.sv:94:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:95:- output logic [7:0] lsu_axi_arlen, design/el2_veer_wrapper.sv:96:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:97:- output logic [2:0] lsu_axi_arsize, design/el2_veer_wrapper.sv:98:-

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:295:- //// AHB LITE BUS design/el2_veer_wrapper.sv:296:- output logic [31:0] haddr, design/el2_veer_wrapper.sv:297:- /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ design/el2_veer_wrapper.sv:298:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:299:- output logic [2:0] hburst, design/el2_veer_wrapper.sv:300:- output logic hmastlock, design/el2_veer_wrapper.sv:301:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:302:- output logic [3:0] hprot, design/el2_veer_wrapper.sv:303:- output logic [2:0] hsize, design/el2_veer_wrapper.sv:304:- output logic [1:0] htrans, design/el2_veer_wrapper.sv:305:- output logic hwrite, design/el2_veer_wrapper.sv:306:- design/el2_veer_wrapper.sv:307:- input logic [63:0] hrdata, design/el2_veer_wrapper.sv:308:- input logic hready, design/el2_veer_wrapper.sv:309:- input logic hresp, design/el2_veer_wrapper.sv:310:- design/el2_veer_wrapper.sv:311:- // LSU AHB Master design/el2_veer_wrapper.sv:312:- output logic [31:0] lsu_haddr, design/el2_veer_wrapper.sv:313:- /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ design/el2_veer_wrapper.sv:314:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:315:- output logic [2:0] lsu_hburst, design/el2_veer_wrapper.sv:316:- output logic lsu_hmastlock, design/el2_veer_wrapper.sv:317:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:318:- output logic [3:0] lsu_hprot, design/el2_veer_wrapper.sv:319:- output logic [2:0] lsu_hsize, design/el2_veer_wrapper.sv:320:- output logic [1:0] lsu_htrans, design/el2_veer_wrapper.sv:321:- output logic lsu_hwrite, design/el2_veer_wrapper.sv:322:- output logic [63:0] lsu_hwdata, design/el2_veer_wrapper.sv:323:- design/el2_veer_wrapper.sv:324:- input logic [63:0] lsu_hrdata, design/el2_veer_wrapper.sv:325:- input logic lsu_hready, design/el2_veer_wrapper.sv:326:- input logic lsu_hresp, design/el2_veer_wrapper.sv:327:- // Debug Syster Bus AHB design/el2_veer_wrapper.sv:328:- output logic [31:0] sb_haddr, design/el2_veer_wrapper.sv:329:- /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ design/el2_veer_wrapper.sv:330:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:331:- output logic [2:0] sb_hburst, design/el2_veer_wrapper.sv:332:- output logic sb_hmastlock, design/el2_veer_wrapper.sv:333:- /*verilator coverage_on*/ design/el2_veer_wrapper.sv:334:- output logic [3:0] sb_hprot, design/el2_veer_wrapper.sv:335:- output logic [2:0] sb_hsize, design/el2_veer_wrapper.sv:336:- output logic [1:0] sb_htrans, design/el2_veer_wrapper.sv:337:- output logic sb_hwrite, design/el2_veer_wrapper.sv:338:- output logic [63:0] sb_hwdata, design/el2_veer_wrapper.sv:339:- design/el2_veer_wrapper.sv:340:- input logic [63:0] sb_hrdata, design/el2_veer_wrapper.sv:341:- input logic sb_hready, design/el2_veer_wrapper.sv:342:- input logic sb_hresp, design/el2_veer_wrapper.sv:343:- design/el2_veer_wrapper.sv:344:- // DMA Slave design/el2_veer_wrapper.sv:345:- input logic dma_hsel, design/el2_veer_wrapper.sv:346:- input logic [31:0] dma_haddr, design/el2_veer_wrapper.sv:347:- input logic [2:0]

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:360:- // clk ratio signals design/el2_veer_wrapper.sv:361:- input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:362:- input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:363:- input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:364:- input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface design/el2_veer_wrapper.sv:365:- design/el2_veer_wrapper.sv:366:- // ICCM/DCCM ECC status design/el2_veer_wrapper.sv:367:- output logic iccm_ecc_single_error, design/el2_veer_wrapper.sv:368:- output logic iccm_ecc_double_error, design/el2_veer_wrapper.sv:369:- output logic dccm_ecc_single_error, design/el2_veer_wrapper.sv:370:- output logic dccm_ecc_double_error, design/el2_veer_wrapper.sv:371:- design/el2_veer_wrapper.sv:372:- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not) design/el2_veer_wrapper.sv:373:- design/el2_veer_wrapper.sv:374:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_veer_wrapper.sv:375:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_veer_wrapper.sv:376:- design/el2_veer_wrapper.sv:377:- input logic timer_int, design/el2_veer_wrapper.sv:378:- input logic soft_int, design/el2_veer_wrapper.sv:379:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer_wrapper.sv:380:- design/el2_veer_wrapper.sv:381:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer_wrapper.sv:382:- output logic dec_tlu_perfcnt1, design/el2_veer_wrapper.sv:383:- output logic dec_tlu_perfcnt2, design/el2_veer_wrapper.sv:384:- output logic dec_tlu_perfcnt3, design/el2_veer_wrapper.sv:385:- design/el2_veer_wrapper.sv:386:- // ports added by the soc team design/el2_veer_wrapper.sv:387:- input logic jtag_tck, // JTAG clk design/el2_veer_wrapper.sv:388:- input logic jtag_tms, // JTAG TMS design/el2_veer_wrapper.sv:389:- input logic jtag_tdi, // JTAG tdi design/el2_veer_wrapper.sv:390:- input logic jtag_trst_n, // JTAG Reset design/el2_veer_wrapper.sv:391:- output logic jtag_tdo, // JTAG TDO design/el2_veer_wrapper.sv:392:- output logic jtag_tdoEn, // JTAG Test Data Output enable design/el2_veer_wrapper.sv:393:- design/el2_veer_wrapper.sv:394:- input logic [31:4] core_id, design/el2_veer_wrapper.sv:395:- design/el2_veer_wrapper.sv:396:- // Memory Export Interface design/el2_veer_wrapper.sv:397:- el2_mem_if.veer_sram_src el2_mem_export, design/el2_veer_wrapper.sv:398:- design/el2_veer_wrapper.sv:399:- // external MPC halt/run interface design/el2_veer_wrapper.sv:400:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer_wrapper.sv:401:- input logic mpc_debug_run_req, // Async run request design/el2_veer_wrapper.sv:402:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer_wrapper.sv:403:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer_wrapper.sv

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:427:- logic active_l2clk; design/el2_veer_wrapper.sv:428:- logic free_l2clk; design/el2_veer_wrapper.sv:426:+ logic active_l2clk; design/el2_veer_wrapper.sv:427:+ logic free_l2clk;