Merge pull request #355 from chipsalliance/qol-improvements

Cleanup VeeR verification codebase
chipsalliance · Jan 18, 2025 · 72b0171 · 72b0171
2 parents 89b9c62 + df970a7
commit 72b0171
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Showing 34 changed files with 229 additions and 70 deletions.
diff --git a/design/dec/el2_dec_tlu_ctl.sv b/design/dec/el2_dec_tlu_ctl.sv
@@ -3174,4 +3174,4 @@ import el2_pkg::*;
                                        );
 
 
-endmodule // dec_timer_ctl
+endmodule // dec_timer_ctl
diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv
@@ -885,6 +885,7 @@ import el2_pkg::*;
                              );
 
 
+   logic unused_dmi_hard_reset;
    //  JTAG/DMI instance
    dmi_wrapper  dmi_wrapper (
     // JTAG signals
@@ -903,7 +904,7 @@ import el2_pkg::*;
     .reg_wr_addr (dmi_addr),        // Write address to Processor
     .reg_en      (dmi_en),          // Write interface bit to Processor
     .reg_wr_en   (dmi_wr_en),       // Write enable to Processor
-    .dmi_hard_reset   ()
+    .dmi_hard_reset   (unused_dmi_hard_reset)
    );
 
    // DMI core/uncore mux

diff --git a/verification/block/common.mk b/verification/block/common.mk
@@ -40,15 +40,22 @@ endif
 ifeq ($(SIM), verilator)
     COMPILE_ARGS += --coverage-max-width 20000
     COMPILE_ARGS += --timing
-    COMPILE_ARGS += -Wall -Wno-fatal
+    COMPILE_ARGS += -Wall
+    COMPILE_ARGS += $(CURDIR)/config.vlt
 
     EXTRA_ARGS   += --trace --trace-structs
     EXTRA_ARGS   += $(VERILATOR_COVERAGE)
     EXTRA_ARGS   += -I$(CFGDIR) -Wno-DECLFILENAME
+
+    # Include test specific Verilator config if it exists
+    ifneq ("$(wildcard $(TEST_DIR)/config.vlt)","")
+        COMPILE_ARGS += $(TEST_DIR)/config.vlt
+    endif
 else ifeq ($(SIM), vcs)
     EXTRA_ARGS   += +incdir+$(CFGDIR) +incdir+$(SRCDIR)/include -assert svaext -cm line+cond+fsm+tgl+branch +vcs+lic+wait
 endif
 
+
 COCOTB_HDL_TIMEUNIT         = 1ns
 COCOTB_HDL_TIMEPRECISION    = 10ps
 
@@ -68,4 +75,3 @@ endif
 # Rules for generating VeeR config
 $(CFGDIR)/common_defines.vh:
 	cd $(CURDIR) && $(CONFIG)/veer.config -fpga_optimize=0 $(EXTRA_CONFIG_OPTS)
-
diff --git a/verification/block/config.vlt b/verification/block/config.vlt
@@ -0,0 +1,99 @@
+`verilator_config
+
+// Unnamed blocks do not influence logic
+lint_off -rule GENUNNAMED
+
+// Unconnected IC memory output pins
+lint_off -rule PINCONNECTEMPTY -file "*/el2_ifu_ic_mem.sv"
+
+// These require revisit to remove multiple definitions of variables with same names
+lint_off -rule VARHIDDEN -file "*/axi4_to_ahb.sv"
+lint_off -rule VARHIDDEN -file "*/el2_ifu_bp_ctl.sv"
+lint_off -rule VARHIDDEN -file "*/el2_ifu_mem_ctl.sv"
+lint_off -rule VARHIDDEN -file "*/el2_exu_alu_ctl.sv"
+lint_off -rule VARHIDDEN -file "*/el2_pic_ctrl.sv"
+
+// Width related warning require explicit type casting
+lint_off -rule WIDTHTRUNC -file "*/ahb_to_axi4.sv"
+lint_off -rule WIDTHTRUNC -file "*/axi4_to_ahb.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dma_ctrl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_ifu_ifc_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_ifu_bp_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_ifu_aln_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_decode_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_tlu_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_lib.sv"
+lint_off -rule WIDTHTRUNC -file "*/beh_lib.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_lsu_bus_buffer.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_pmp_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_lsu_addrcheck.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_lsu_trigger.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_ifu_iccm_mem.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_ifu_mem_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_exu.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_dbg.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_pic_ctrl.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_pmp.sv"
+lint_off -rule WIDTHTRUNC -file "*/el2_mem_if.sv"
+
+lint_off -rule WIDTHEXPAND -file "*/el2_exu.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_pic_ctrl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_ifu_bp_ctl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_ifu_mem_ctl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_ifu_iccm_mem.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_lsu_addrcheck.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_lsu_bus_buffer.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_lsu_stbuf.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_lsu_dccm_ctl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_lsu_dccm_mem.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_exu_mul_ctl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_dec_tlu_ctl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_dma_ctrl.sv"
+lint_off -rule WIDTHEXPAND -file "*/el2_dbg.sv"
+
+// Unused parameters are probably safe to remove from RTL
+lint_off -rule UNUSEDPARAM -file "*/axi4_to_ahb.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_ifu.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_pic_ctrl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_dma_ctrl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_ifu_bp_ctl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_ifu_mem_ctl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_dec_tlu_ctl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_lsu_dccm_ctl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_lsu_dccm_mem.sv"
+
+// Gated clock, expected latch
+lint_off -rule LATCH -file "*/beh_lib.sv" -lines 781
+
+lint_off -rule BLKSEQ -file "*/beh_lib.sv" -lines 783
+
+// The Verilator reports that `core_rst_l` is being used in sync and async nets,
+// pointing to `rvdff` module as a source of the problem. Since the `rvdff` looks
+// unrelated to `core_rst_l`, it requires a closer investigation.
+lint_off -rule SYNCASYNCNET -file "*/el2_veer.sv" -lines 35
+
+// Logic that might be not optimal for event based model used by Verilator
+lint_off -rule UNOPTFLAT -file "*/axi4_to_ahb.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_ifu_ifc_ctl.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_dec_decode_ctl.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_exu_mul_ctl.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_exu_div_ctl.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_lsu.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_lsu_lsc_ctl.sv"
+lint_off -rule UNOPTFLAT -file "*/el2_pic_ctrl.sv"
+
+// Warnings related to the generated `el2_param.vh`
+lint_off -rule UNUSEDPARAM -file "*/el2_ifu_compress_ctl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_dec_gpr_ctl.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_lsu_trigger.sv"
+lint_off -rule UNUSEDPARAM -file "*/el2_lsu_clkdomain.sv"
+
+lint_off -rule WIDTHTRUNC -file "*/el2_ifu_compress_ctl.sv"
diff --git a/verification/block/dccm/Makefile b/verification/block/dccm/Makefile
@@ -3,8 +3,8 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
@@ -13,12 +13,12 @@ TOPLEVEL     = el2_lsu_dccm_mem_wrapper
 
 VERILOG_SOURCES  = \
     $(SRCDIR)/lib/el2_mem_if.sv \
-    $(CURDIR)/dccm/el2_lsu_dccm_mem_wrapper.sv \
+    $(TEST_DIR)/el2_lsu_dccm_mem_wrapper.sv \
     $(SRCDIR)/lsu/el2_lsu_dccm_mem.sv \
     $(SRCDIR)/lib/mem_lib.sv
 
 # Undefine the VERILATOR macro to make the code use actual RAM cells instead
 # of simulation models
 EXTRA_ARGS += -UVERILATOR
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/dccm/config.vlt b/verification/block/dccm/config.vlt
@@ -0,0 +1,7 @@
+`verilator_config
+
+lint_off -rule PINCONNECTEMPTY -file "*/el2_lsu_dccm_mem_wrapper.sv"
+
+lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem_wrapper.sv"
+
+lint_off -rule IMPORTSTAR -file "*/el2_mem_if.sv"
diff --git a/verification/block/dec_ib/Makefile b/verification/block/dec_ib/Makefile
@@ -2,16 +2,16 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = el2_dec_ib_ctl_wrapper
 
 VERILOG_SOURCES  = \
-    $(CURDIR)/dec_ib/el2_dec_ib_ctl_wrapper.sv \
+    $(TEST_DIR)/el2_dec_ib_ctl_wrapper.sv \
     $(SRCDIR)/dec/el2_dec_ib_ctl.sv
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/dec_ib/config.vlt b/verification/block/dec_ib/config.vlt
@@ -0,0 +1,3 @@
+`verilator_config
+
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl_wrapper.sv"
diff --git a/verification/block/dec_tl/Makefile b/verification/block/dec_tl/Makefile
@@ -2,16 +2,16 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = el2_dec_trigger_wrapper
 
 VERILOG_SOURCES  = \
-    $(CURDIR)/dec_tl/el2_dec_trigger_wrapper.sv \
+    $(TEST_DIR)/el2_dec_trigger_wrapper.sv \
     $(SRCDIR)/dec/el2_dec_trigger.sv
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/dec_tl/config.vlt b/verification/block/dec_tl/config.vlt
@@ -0,0 +1,5 @@
+`verilator_config
+
+lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger_wrapper.sv"
+
+lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger_wrapper.sv"
diff --git a/verification/block/dma/Makefile b/verification/block/dma/Makefile
@@ -3,8 +3,8 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
@@ -14,4 +14,4 @@ TOPLEVEL     = el2_dma_ctrl
 VERILOG_SOURCES  = \
     $(SRCDIR)/el2_dma_ctrl.sv
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/dmi/Makefile b/verification/block/dmi/Makefile
@@ -2,20 +2,20 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = dmi_test_wrapper
 
 VERILOG_SOURCES  = \
-    $(CURDIR)/dmi/dmi_test_wrapper.sv \
+    $(TEST_DIR)/dmi_test_wrapper.sv \
     $(SRCDIR)/dmi/rvjtag_tap.v \
     $(SRCDIR)/dmi/dmi_mux.v \
     $(SRCDIR)/dmi/dmi_jtag_to_core_sync.v \
     $(SRCDIR)/dmi/dmi_wrapper.v
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
 
diff --git a/verification/block/dmi/config.vlt b/verification/block/dmi/config.vlt
@@ -0,0 +1,5 @@
+`verilator_config
+
+lint_off -rule WIDTHTRUNC -file "*/dmi_test_wrapper.sv"
+
+lint_off -rule UNUSEDPARAM -file "*/dmi_test_wrapper.sv"
diff --git a/verification/block/exu_alu/Makefile b/verification/block/exu_alu/Makefile
@@ -3,16 +3,16 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = el2_exu_alu_ctl_wrapper
 
 VERILOG_SOURCES  = \
-    $(CURDIR)/exu_alu/el2_exu_alu_ctl_wrapper.sv \
+    $(TEST_DIR)/el2_exu_alu_ctl_wrapper.sv \
     $(SRCDIR)/exu/el2_exu_alu_ctl.sv
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/exu_alu/config.vlt b/verification/block/exu_alu/config.vlt
@@ -0,0 +1,5 @@
+`verilator_config
+
+lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl_wrapper.sv"
+
+lint_off -rule UNUSEDPARAM -file "*/el2_exu_alu_ctl_wrapper.sv"
diff --git a/verification/block/exu_div/Makefile b/verification/block/exu_div/Makefile
@@ -3,16 +3,16 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = el2_exu_div_ctl_wrapper
 
 VERILOG_SOURCES  = \
-    $(CURDIR)/exu_div/el2_exu_div_ctl_wrapper.sv \
+    $(TEST_DIR)/el2_exu_div_ctl_wrapper.sv \
     $(SRCDIR)/exu/el2_exu_div_ctl.sv
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/exu_div/config.vlt b/verification/block/exu_div/config.vlt
@@ -0,0 +1,5 @@
+`verilator_config
+
+lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl_wrapper.sv"
+
+lint_off -rule UNUSEDPARAM -file "*/el2_exu_div_ctl_wrapper.sv"
diff --git a/verification/block/exu_mul/Makefile b/verification/block/exu_mul/Makefile
@@ -3,16 +3,16 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = el2_exu_mul_ctl_wrapper
 
 VERILOG_SOURCES  = \
-    $(CURDIR)/exu_mul/el2_exu_mul_ctl_wrapper.sv \
+    $(TEST_DIR)/el2_exu_mul_ctl_wrapper.sv \
     $(SRCDIR)/exu/el2_exu_mul_ctl.sv
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
diff --git a/verification/block/exu_mul/config.vlt b/verification/block/exu_mul/config.vlt
@@ -0,0 +1,5 @@
+`verilator_config
+
+lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl_wrapper.sv"
+
+lint_off -rule UNUSEDPARAM -file "*/el2_exu_mul_ctl_wrapper.sv"
diff --git a/verification/block/iccm/Makefile b/verification/block/iccm/Makefile
@@ -3,8 +3,8 @@ null  :=
 space := $(null) #
 comma := ,
 
-CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-SRCDIR := $(abspath $(CURDIR)../../../../design)
+TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(TEST_DIR)../../../../design)
 
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
@@ -13,12 +13,12 @@ TOPLEVEL     = el2_ifu_iccm_mem_wrapper
 
 VERILOG_SOURCES  = \
     $(SRCDIR)/lib/el2_mem_if.sv \
-    $(CURDIR)/iccm/el2_ifu_iccm_mem_wrapper.sv \
+    $(TEST_DIR)/el2_ifu_iccm_mem_wrapper.sv \
     $(SRCDIR)/ifu/el2_ifu_iccm_mem.sv \
     $(SRCDIR)/lib/mem_lib.sv
 
 # Undefine the VERILATOR macro to make the code use actual RAM cells instead
 # of simulation models
 EXTRA_ARGS += -UVERILATOR
 
-include $(CURDIR)/../common.mk
+include $(TEST_DIR)/../common.mk
Original file line number	Diff line number	Diff line change
Expand Up		@@ -3174,4 +3174,4 @@ import el2_pkg::*;
		);


		endmodule // dec_timer_ctl
		endmodule // dec_timer_ctl
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,3 @@
		`verilator_config

		lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl_wrapper.sv"