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@wsipak
wsipak committed Oct 8, 2024
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<span id="L28"><span class="lineNum"> 28</span> : )</span>
<span id="L29"><span class="lineNum"> 29</span> : // ,TAG = 1)</span>
<span id="L30"><span class="lineNum"> 30</span> : (</span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC tlaBgGNC"> 43285336 : input clk,</span></span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC tlaBgGNC"> 43285400 : input clk,</span></span>
<span id="L32"><span class="lineNum"> 32</span> <span class="tlaGNC"> 36 : input rst_l,</span></span>
<span id="L33"><span class="lineNum"> 33</span> <span class="tlaUNC tlaBgUNC"> 0 : input scan_mode,</span></span>
<span id="L34"><span class="lineNum"> 34</span> <span class="tlaGNC tlaBgGNC"> 24 : input bus_clk_en,</span></span>
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<span id="L159"><span class="lineNum"> 159</span> <span class="tlaGNC"> 24 : buf_read_error_in = 1'b0; // signal indicating that an error came back with the read from the core</span></span>
<span id="L160"><span class="lineNum"> 160</span> <span class="tlaGNC"> 24 : cmdbuf_wr_en = 1'b0; // all clear from the gasket to load the buffer with the command for reads, command/dat for writes</span></span>
<span id="L161"><span class="lineNum"> 161</span> <span class="tlaGNC"> 24 : case (buf_state)</span></span>
<span id="L162"><span class="lineNum"> 162</span> <span class="tlaGNC"> 14981480 : IDLE: begin // No commands recieved</span></span>
<span id="L163"><span class="lineNum"> 163</span> <span class="tlaGNC"> 14981480 : buf_nxtstate = ahb_hwrite ? WR : RD;</span></span>
<span id="L164"><span class="lineNum"> 164</span> <span class="tlaGNC"> 14981480 : buf_state_en = ahb_hready &amp; ahb_htrans[1] &amp; ahb_hsel; // only transition on a valid hrtans</span></span>
<span id="L162"><span class="lineNum"> 162</span> <span class="tlaGNC"> 14904566 : IDLE: begin // No commands recieved</span></span>
<span id="L163"><span class="lineNum"> 163</span> <span class="tlaGNC"> 14904566 : buf_nxtstate = ahb_hwrite ? WR : RD;</span></span>
<span id="L164"><span class="lineNum"> 164</span> <span class="tlaGNC"> 14904566 : buf_state_en = ahb_hready &amp; ahb_htrans[1] &amp; ahb_hsel; // only transition on a valid hrtans</span></span>
<span id="L165"><span class="lineNum"> 165</span> : end</span>
<span id="L166"><span class="lineNum"> 166</span> <span class="tlaGNC"> 2210 : WR: begin // Write command recieved last cycle</span></span>
<span id="L167"><span class="lineNum"> 167</span> <span class="tlaGNC"> 2210 : buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite ? WR : RD;</span></span>
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<tr>
<td class="headerInfo">Test Date:</td>
<td class="headerInfoValue">
07-10-2024
08-10-2024
</td>
<td></td>

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<span id="L27"><span class="lineNum"> 27</span> : `include "el2_param.vh"</span>
<span id="L28"><span class="lineNum"> 28</span> : ,parameter TAG = 1) (</span>
<span id="L29"><span class="lineNum"> 29</span> : </span>
<span id="L30"><span class="lineNum"> 30</span> <span class="tlaGNC tlaBgGNC"> 40602267 : input clk,</span></span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC"> 40602267 : input free_clk,</span></span>
<span id="L30"><span class="lineNum"> 30</span> <span class="tlaGNC tlaBgGNC"> 40602331 : input clk,</span></span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC"> 40602331 : input free_clk,</span></span>
<span id="L32"><span class="lineNum"> 32</span> <span class="tlaGNC"> 25 : input rst_l,</span></span>
<span id="L33"><span class="lineNum"> 33</span> <span class="tlaUNC tlaBgUNC"> 0 : input scan_mode,</span></span>
<span id="L34"><span class="lineNum"> 34</span> <span class="tlaGNC tlaBgGNC"> 25 : input bus_clk_en,</span></span>
Expand Down Expand Up @@ -392,18 +392,18 @@
<span id="L288"><span class="lineNum"> 288</span> <span class="tlaGNC"> 25 : rd_bypass_idle = 1'b0;</span></span>
<span id="L289"><span class="lineNum"> 289</span> : </span>
<span id="L290"><span class="lineNum"> 290</span> <span class="tlaGNC"> 25 : case (buf_state)</span></span>
<span id="L291"><span class="lineNum"> 291</span> <span class="tlaGNC"> 14962499 : IDLE: begin</span></span>
<span id="L292"><span class="lineNum"> 292</span> <span class="tlaGNC"> 14962499 : master_ready = 1'b1;</span></span>
<span id="L293"><span class="lineNum"> 293</span> <span class="tlaGNC"> 14962499 : buf_write_in = (master_opc[2:1] == 2'b01);</span></span>
<span id="L294"><span class="lineNum"> 294</span> <span class="tlaGNC"> 14962499 : buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;</span></span>
<span id="L295"><span class="lineNum"> 295</span> <span class="tlaGNC"> 14962499 : buf_state_en = master_valid &amp; master_ready;</span></span>
<span id="L296"><span class="lineNum"> 296</span> <span class="tlaGNC"> 14962499 : buf_wr_en = buf_state_en;</span></span>
<span id="L297"><span class="lineNum"> 297</span> <span class="tlaGNC"> 14962499 : buf_data_wr_en = buf_state_en &amp; (buf_nxtstate == CMD_WR);</span></span>
<span id="L298"><span class="lineNum"> 298</span> <span class="tlaGNC"> 14962499 : buf_cmd_byte_ptr_en = buf_state_en;</span></span>
<span id="L299"><span class="lineNum"> 299</span> <span class="tlaGNC"> 14962499 : buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];</span></span>
<span id="L300"><span class="lineNum"> 300</span> <span class="tlaGNC"> 14962499 : bypass_en = buf_state_en;</span></span>
<span id="L301"><span class="lineNum"> 301</span> <span class="tlaGNC"> 14962499 : rd_bypass_idle = bypass_en &amp; (buf_nxtstate == CMD_RD);</span></span>
<span id="L302"><span class="lineNum"> 302</span> <span class="tlaGNC"> 14962499 : ahb_htrans[1:0] = {2{bypass_en}} &amp; 2'b10;</span></span>
<span id="L291"><span class="lineNum"> 291</span> <span class="tlaGNC"> 14885585 : IDLE: begin</span></span>
<span id="L292"><span class="lineNum"> 292</span> <span class="tlaGNC"> 14885585 : master_ready = 1'b1;</span></span>
<span id="L293"><span class="lineNum"> 293</span> <span class="tlaGNC"> 14885585 : buf_write_in = (master_opc[2:1] == 2'b01);</span></span>
<span id="L294"><span class="lineNum"> 294</span> <span class="tlaGNC"> 14885585 : buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;</span></span>
<span id="L295"><span class="lineNum"> 295</span> <span class="tlaGNC"> 14885585 : buf_state_en = master_valid &amp; master_ready;</span></span>
<span id="L296"><span class="lineNum"> 296</span> <span class="tlaGNC"> 14885585 : buf_wr_en = buf_state_en;</span></span>
<span id="L297"><span class="lineNum"> 297</span> <span class="tlaGNC"> 14885585 : buf_data_wr_en = buf_state_en &amp; (buf_nxtstate == CMD_WR);</span></span>
<span id="L298"><span class="lineNum"> 298</span> <span class="tlaGNC"> 14885585 : buf_cmd_byte_ptr_en = buf_state_en;</span></span>
<span id="L299"><span class="lineNum"> 299</span> <span class="tlaGNC"> 14885585 : buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];</span></span>
<span id="L300"><span class="lineNum"> 300</span> <span class="tlaGNC"> 14885585 : bypass_en = buf_state_en;</span></span>
<span id="L301"><span class="lineNum"> 301</span> <span class="tlaGNC"> 14885585 : rd_bypass_idle = bypass_en &amp; (buf_nxtstate == CMD_RD);</span></span>
<span id="L302"><span class="lineNum"> 302</span> <span class="tlaGNC"> 14885585 : ahb_htrans[1:0] = {2{bypass_en}} &amp; 2'b10;</span></span>
<span id="L303"><span class="lineNum"> 303</span> : end</span>
<span id="L304"><span class="lineNum"> 304</span> <span class="tlaGNC"> 1912 : CMD_RD: begin</span></span>
<span id="L305"><span class="lineNum"> 305</span> <span class="tlaGNC"> 1912 : buf_nxtstate = (master_valid &amp; (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;</span></span>
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