[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dec/el2_dec_pmp_ctl.sv:116:- rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk), design/dec/el2_dec_pmp_ctl.sv:117:- .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~entry_lock_eff[entry_idx])), design/dec/el2_dec_pmp_ctl.sv:118:- .din(csr_wdata), design/dec/el2_dec_pmp_ctl.sv:119:- .dout(pmp_pmpcfg[entry_idx])); design/dec/el2_dec_pmp_ctl.sv:120:- end design/dec/el2_dec_pmp_ctl.sv:121:- design/dec/el2_dec_pmp_ctl.sv:122:- // ---------------------------------------------------------------------- design/dec/el2_dec_pmp_ctl.sv:123:- // PMPADDRx (RW) design/dec/el2_dec_pmp_ctl.sv:124:- // [31:0] : PMP entry (x) address selector (word addressing) design/dec/el2_dec_pmp_ctl.sv:125:- // design/dec/el2_dec_pmp_ctl.sv:126:- // NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping design/dec/el2_dec_pmp_ctl.sv:127:- // to bits 33:32 of the physical address are always set to 0. (WARL) design/dec/el2_dec_pmp_ctl.sv:128:- design/dec/el2_dec_pmp_ctl.sv:129:- localparam PMPADDR0 = 12'h3b0; design/dec/el2_dec_pmp_ctl.sv:130:- localparam PMPADDR16 = 12'h3c0; design/dec/el2_dec_pmp_ctl.sv:131:- localparam PMPADDR32 = 12'h3d0; design/dec/el2_dec_pmp_ctl.sv:132:- localparam PMPADDR48 = 12'h3e0; design/dec/el2_dec_pmp_ctl.sv:133:- design/dec/el2_dec_pmp_ctl.sv:134:- assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4]; design/dec/el2_dec_pmp_ctl.sv:135:- assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4]; design/dec/el2_dec_pmp_ctl.sv:136:- assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4]; design/dec/el2_dec_pmp_ctl.sv:137:- assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4]; design/dec/el2_dec_pmp_ctl.sv:138:- assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel); design/dec/el2_dec_pmp_ctl.sv:139:- design/dec/el2_dec_pmp_ctl.sv:140:- assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel; design/dec/el2_dec_pmp_ctl.sv:141:- assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel; design/dec/el2_dec_pmp_ctl.sv:142:- assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address design/dec/el2_dec_pmp_ctl.sv:143:- design/dec/el2_dec_pmp_ctl.sv:144:- for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff design/dec/el2_dec_pmp_ctl.sv:145:- logic pmpaddr_lock; design/dec/el2_dec_pmp_ctl.sv:146:- logic pmpaddr_lock_next; design/dec/el2_dec_pmp_ctl.sv:147:- if (entry_idx+1 < pt.PMP_ENTRIES) design/dec/el2_dec_pmp_ctl.sv:148:- assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR; design/dec/el2_dec_pmp_ctl.sv:149:- else design/dec/el2_dec_pmp_ctl.sv:150:- assign pmpaddr_lock_next = 1'b0; design/dec/el2_dec_pmp_ctl.sv:151:- assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next; design/dec/el2_dec_pmp_ctl.sv:152:- assign pmp_pmpaddr[entry_idx][31:30] = 2'b00; design/dec/el2_dec_pmp_ctl.sv:153:- rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk), design/dec/el2_dec_pmp_ctl.sv:154:- .en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx) design/dec/el2_dec_pmp_ctl.sv:155:- & (~pmpaddr_lock)), design/dec/el2_dec_pmp_ctl.sv:156:- .din(dec_csr_wrdata_r[29:0]), design/dec/el2_dec_pmp_ctl.sv:157:- .dout(pmp_pmpaddr[entry_idx][29:0])); design/dec/el2_dec_pmp_ctl.sv:158:- end design/dec/el2_dec_pmp_ctl.sv:159:- design/dec/el2_dec_pmp_ctl.sv:160:- // CSR read mux design/dec/el2_dec_pmp_ctl.sv:161:- design/dec/el2_dec_pmp_ctl.sv:162:- assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0]; design/dec/el2_dec_pmp_ctl.sv:163:- assign pmp_pmpcfg_rddata = { pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}], design