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Exclude some signals from coverage #239

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Exclude some signals from coverage #239

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a861113
fix renode version
wsipak Oct 3, 2024
b10d1b3
exclude signals from coverage
wsipak Oct 3, 2024
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6 changes: 3 additions & 3 deletions .github/workflows/get-renode.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ jobs:
runs-on: ubuntu-latest
env:
TOOL_NAME: renode
TOOL_VERSION: latest
TOOL_VERSION: 1.15.3+20240924gitc7bc336bb
DEBIAN_FRONTEND: "noninteractive"

steps:
Expand All @@ -37,10 +37,10 @@ jobs:
key: ${{ env.cache_name }}_${{ env.cache_date }}
restore-keys: ${{ env.cache_name }}_

- name: Get latest nightly release
- name: Get Renode
if: ${{ steps.cache.outputs.cache-hit != 'true' }}
run: |
wget https://builds.renode.io/renode-latest.linux-portable.tar.gz
wget https://builds.renode.io/renode-${{ env.TOOL_VERSION}}.linux-portable.tar.gz

- name: Rename the archive
if: ${{ steps.cache.outputs.cache-hit != 'true' }}
Expand Down
4 changes: 4 additions & 0 deletions design/dbg/el2_dbg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@
module el2_dbg
import el2_pkg::*;
#(
`include "el2_param.vh"

Check warning on line 27 in design/dbg/el2_dbg.sv

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/dbg/el2_dbg.sv:27:-`include "el2_param.vh"
design/dbg/el2_dbg.sv:28:- )(
design/dbg/el2_dbg.sv:29:-   // outputs to the core for command and data interface
design/dbg/el2_dbg.sv:30:-   output logic [31:0]                 dbg_cmd_addr,
design/dbg/el2_dbg.sv:31:-   output logic [31:0]                 dbg_cmd_wrdata,
design/dbg/el2_dbg.sv:32:-   output logic                        dbg_cmd_valid,
design/dbg/el2_dbg.sv:33:-   output logic                        dbg_cmd_write,             // 1: write command, 0: read_command
design/dbg/el2_dbg.sv:34:-   output logic [1:0]                  dbg_cmd_type,              // 0:gpr 1:csr 2: memory
design/dbg/el2_dbg.sv:35:-   output logic [1:0]                  dbg_cmd_size,              // size of the abstract mem access debug command
design/dbg/el2_dbg.sv:36:-   output logic                        dbg_core_rst_l,            // core reset from dm
design/dbg/el2_dbg.sv:37:-
design/dbg/el2_dbg.sv:38:-   // inputs back from the core/dec
design/dbg/el2_dbg.sv:39:-   input logic [31:0]                  core_dbg_rddata,
design/dbg/el2_dbg.sv:40:-   input logic                         core_dbg_cmd_done,         // This will be treated like a valid signal
design/dbg/el2_dbg.sv:41:-   input logic                         core_dbg_cmd_fail,         // Exception during command run
design/dbg/el2_dbg.sv:42:-
design/dbg/el2_dbg.sv:43:-   // Signals to dma to get a bubble
design/dbg/el2_dbg.sv:44:-   output logic                        dbg_dma_bubble,            // Debug needs a bubble to send a valid
design/dbg/el2_dbg.sv:45:-   input  logic                        dma_dbg_ready,             // DMA is ready to accept debug request
design/dbg/el2_dbg.sv:46:-
design/dbg/el2_dbg.sv:47:-   // interface with the rest of the core to halt/resume handshaking
design/dbg/el2_dbg.sv:48:-   output logic                        dbg_halt_req,              // This is a pulse
design/dbg/el2_dbg.sv:49:-   output logic                        dbg_resume_req,            // Debug sends a resume requests. Pulse
design/dbg/el2_dbg.sv:50:-   input  logic                        dec_tlu_debug_mode,        // Core is in debug mode
design/dbg/el2_dbg.sv:51:-   input  logic                        dec_tlu_dbg_halted,        // The core has finished the queiscing sequence. Core is halted now
design/dbg/el2_dbg.sv:52:-   input  logic                        dec_tlu_mpc_halted_only,   // Only halted due to MPC
design/dbg/el2_dbg.sv:53:-   input  logic                        dec_tlu_resume_ack,        // core sends back an ack for the resume (pulse)
design/dbg/el2_dbg.sv:54:-
design/dbg/el2_dbg.sv:55:-   // inputs from the JTAG
design/dbg/el2_dbg.sv:56:-   input logic                         dmi_reg_en,                // read or write
design/dbg/el2_dbg.sv:57:-   input logic [6:0]                   dmi_reg_addr,              // address of DM register
design/dbg/el2_dbg.sv:58:-   input logic                         dmi_reg_wr_en,             // write instruction
design/dbg/el2_dbg.sv:59:-   input logic [31:0]                  dmi_reg_wdata,             // write data
design/dbg/el2_dbg.sv:60:-
design/dbg/el2_dbg.sv:61:-   // output
design/dbg/el2_dbg.sv:62:-   output logic [31:0]                 dmi_reg_rdata,             // read data
design/dbg/el2_dbg.sv:63:-
design/dbg/el2_dbg.sv:64:-   // AXI Write Channels
design/dbg/el2_dbg.sv:65:-   output logic                        sb_axi_awvalid,
design/dbg/el2_dbg.sv:66:-   input  logic                        sb_axi_awready,
design/dbg/el2_dbg.sv:67:-   /*verilator coverage_off*/
design/dbg/el2_dbg.sv:68:-   output logic [pt.SB_BUS_TAG-1:0]    sb_axi_awid,
design/dbg/el2_dbg.sv:69:-   /*verilator coverage_on*/
design/dbg/el2_dbg.sv:70:-   output logic [31:0]                 sb_axi_awaddr,
design/dbg/el2_dbg.sv:71:-   output logic [3:0]                  sb_axi_awregion,
design/dbg/el2_dbg.sv:72:-   /*verilator coverage_off*/
design/dbg/el2_dbg.sv:73:-   output logic [7:0]                  sb_axi_awlen,
design/dbg/el2_dbg.
)(
// outputs to the core for command and data interface
output logic [31:0] dbg_cmd_addr,
Expand Down Expand Up @@ -64,13 +64,17 @@
// AXI Write Channels
output logic sb_axi_awvalid,
input logic sb_axi_awready,
/*verilator coverage_off*/
output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
/*verilator coverage_on*/
output logic [31:0] sb_axi_awaddr,
output logic [3:0] sb_axi_awregion,
/*verilator coverage_off*/
output logic [7:0] sb_axi_awlen,
output logic [2:0] sb_axi_awsize,
output logic [1:0] sb_axi_awburst,
output logic sb_axi_awlock,
/*verilator coverage_on*/
output logic [3:0] sb_axi_awcache,
output logic [2:0] sb_axi_awprot,
output logic [3:0] sb_axi_awqos,
Expand Down
2 changes: 2 additions & 0 deletions design/ifu/el2_ifu_mem_ctl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@
module el2_ifu_mem_ctl
import el2_pkg::*;
#(
`include "el2_param.vh"

Check warning on line 27 in design/ifu/el2_ifu_mem_ctl.sv

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:27:-`include "el2_param.vh"
design/ifu/el2_ifu_mem_ctl.sv:28:- )
design/ifu/el2_ifu_mem_ctl.sv:29:-  (
design/ifu/el2_ifu_mem_ctl.sv:30:-   input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
design/ifu/el2_ifu_mem_ctl.sv:31:-   input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
design/ifu/el2_ifu_mem_ctl.sv:32:-   input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
design/ifu/el2_ifu_mem_ctl.sv:33:-   input logic rst_l,                                               // reset, active low
design/ifu/el2_ifu_mem_ctl.sv:34:-
design/ifu/el2_ifu_mem_ctl.sv:35:-   input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
design/ifu/el2_ifu_mem_ctl.sv:36:-   input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
design/ifu/el2_ifu_mem_ctl.sv:37:-   input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
design/ifu/el2_ifu_mem_ctl.sv:38:-   input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
design/ifu/el2_ifu_mem_ctl.sv:39:-   input logic                       dec_tlu_force_halt,            // force halt.
design/ifu/el2_ifu_mem_ctl.sv:40:-
design/ifu/el2_ifu_mem_ctl.sv:41:-   input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
design/ifu/el2_ifu_mem_ctl.sv:42:-   input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
design/ifu/el2_ifu_mem_ctl.sv:43:-   input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
design/ifu/el2_ifu_mem_ctl.sv:44:-   input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
design/ifu/el2_ifu_mem_ctl.sv:45:-   input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
design/ifu/el2_ifu_mem_ctl.sv:46:-   input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
design/ifu/el2_ifu_mem_ctl.sv:47:-   input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
design/ifu/el2_ifu_mem_ctl.sv:48:-   input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
design/ifu/el2_ifu_mem_ctl.sv:49:-   input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
design/ifu/el2_ifu_mem_ctl.sv:50:-
design/ifu/el2_ifu_mem_ctl.sv:51:-   input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
design/ifu/el2_ifu_mem_ctl.sv:52:-
design/ifu/el2_ifu_mem_ctl.sv:53:-   output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
design/ifu/el2_ifu_mem_ctl.sv:54:-   output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
design/ifu/el2_ifu_mem_ctl.sv:55:-   output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
design/ifu/el2_ifu_mem_ctl.sv:56:-   output logic                      ic_write_stall,                // Stall fetch the cycle we are writing th
)
(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
Expand Down Expand Up @@ -64,6 +64,7 @@

//-------------------------- IFU AXI signals--------------------------
// AXI Write Channels
/*verilator coverage_off*/
output logic ifu_axi_awvalid,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
output logic [31:0] ifu_axi_awaddr,
Expand All @@ -75,6 +76,7 @@
output logic [3:0] ifu_axi_awcache,
output logic [2:0] ifu_axi_awprot,
output logic [3:0] ifu_axi_awqos,
/*verilator coverage_on*/

output logic ifu_axi_wvalid,
output logic [63:0] ifu_axi_wdata,
Expand Down
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