Exclude signals tied to constant values #247

wsipak · 2024-10-15T08:53:01Z

No description provided.

github-actions · 2024-10-15T08:54:02Z

design/dec/el2_dec_decode_ctl.sv

@@ -196,7 +196,10 @@ import el2_pkg::*;

   output logic       dec_div_active,                 // non-block divide is active


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic dec_div_active, // non-block divide is active

output logic dec_i0_alu_decode_d, // decode to D-stage alu

output logic dec_i0_branch_d, // Branch in D-stage

github-actions · 2024-10-15T08:54:02Z

design/dec/el2_dec_decode_ctl.sv

+   /* exclude signals that are tied to constant value in tb_top.sv */
+   /*verilator coverage_off*/
   input  logic       scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

output logic [ 4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's

output logic dec_i0_wen_r, // i0 write enable

output logic [31:0] dec_i0_wdata_r, // i0 write data

github-actions · 2024-10-15T08:54:02Z

design/dec/el2_dec_decode_ctl.sv

   input  logic       scan_mode
+   /*verilator coverage_on*/
   );




[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches

github-actions · 2024-10-15T08:54:02Z

design/dec/el2_dec_gpr_ctl.sv

@@ -39,7 +39,10 @@ import el2_pkg::*;
    output logic [31:0] rd0,         // read data


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [31:0] rd0, // read data

output logic [31:0] rd0, // read data

github-actions · 2024-10-15T08:54:02Z

design/dec/el2_dec_gpr_ctl.sv

+   /* exclude signals that are tied to constant value in tb_top.sv */
+   /*verilator coverage_off*/
    input  logic        scan_mode
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

github-actions · 2024-10-15T08:54:03Z

design/ifu/el2_ifu_bp_ctl.sv

@@ -75,7 +75,10 @@ import el2_pkg::*;

   output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)

logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;

logic [1:0] bht_bank0_rd_data_f;

logic [1:0] bht_bank1_rd_data_f;

logic [1:0] bht_bank0_rd_data_p1_f;

genvar j, i;

github-actions · 2024-10-15T08:54:03Z

design/ifu/el2_ifu_bp_ctl.sv

+   /* exclude signals that are tied to constant value in tb_top.sv */
+   /*verilator coverage_off*/
   input  logic       scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict

assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset

assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst

assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst

assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst

assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always

assign exu_mp_way = exu_mp_pkt.way; // repl way

assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history

assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0]; // target offset

assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address

assign exu_mp_ataken = exu_mp_pkt.ataken;

github-actions · 2024-10-15T08:54:04Z

design/ifu/el2_ifu_ifc_ctl.sv

   input logic rst_l, // reset enable, from core pin
+   /* exclude signals that are tied to constant value in tb_top.sv */
+   /*verilator coverage_off*/
   input logic scan_mode, // scan
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic rst_l, // reset enable, from core pin

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode, // scan

/*verilator coverage_on*/

input logic rst_l, // reset enable, from core pin

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode, // scan

/*verilator coverage_on*/

github-actions · 2024-10-15T08:54:04Z

design/ifu/el2_ifu_ifc_ctl.sv

   input logic ic_hit_f,      // Icache hit
   input logic ifu_ic_mb_empty, // Miss buffer empty


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic ic_hit_f, // Icache hit

input logic ifu_ic_mb_empty, // Miss buffer empty

input logic ic_hit_f, // Icache hit

input logic ifu_ic_mb_empty, // Miss buffer empty

github-actions · 2024-10-15T08:54:04Z

design/lsu/el2_lsu_addrcheck.sv

+   /* exclude signals that are tied to constant value in tb_top.sv */
+   /*verilator coverage_off*/
   input  logic         scan_mode                  // Scan mode
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode // Scan mode

/*verilator coverage_on*/

/* exclude signals that are tied to constant value in tb_top.sv */

/*verilator coverage_off*/

input logic scan_mode // Scan mode

/*verilator coverage_on*/

github-actions · 2024-10-15T11:39:17Z

Links to coverage and verification reports for this PR (#247) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-15T16:14:06Z

Links to coverage and verification reports for this PR (#247) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-16T10:07:51Z

Links to coverage and verification reports for this PR (#247) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-16T10:24:52Z

design/dec/el2_dec_decode_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input  logic       scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

output logic [ 4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's

output logic dec_i0_wen_r, // i0 write enable

output logic [31:0] dec_i0_wdata_r, // i0 write data

github-actions · 2024-10-16T10:24:52Z

design/dec/el2_dec_gpr_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
    input  logic        scan_mode
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

github-actions · 2024-10-16T10:24:52Z

design/dec/el2_dec_pmp_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input  logic        scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

github-actions · 2024-10-16T10:24:53Z

design/ifu/el2_ifu.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input logic scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

github-actions · 2024-10-16T10:24:53Z

design/ifu/el2_ifu_aln_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input logic                                    scan_mode,                // Flop scan mode control
+   /*verilator coverage_on*/
   input logic                                    rst_l,                    // reset, active low
   input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
   input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode, // Flop scan mode control

/*verilator coverage_on*/

input logic rst_l, // reset, active low

input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.

input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode, // Flop scan mode control

/*verilator coverage_on*/

input logic rst_l, // reset, active low

input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.

input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.

github-actions · 2024-10-16T10:24:53Z

design/ifu/el2_ifu_bp_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input  logic       scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict

assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset

assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst

assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst

assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst

assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always

assign exu_mp_way = exu_mp_pkt.way; // repl way

assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history

assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0]; // target offset

assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address

assign exu_mp_ataken = exu_mp_pkt.ataken;

github-actions · 2024-10-16T10:24:53Z

design/ifu/el2_ifu_ifc_ctl.sv

   input logic rst_l, // reset enable, from core pin
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input logic scan_mode, // scan
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic rst_l, // reset enable, from core pin

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode, // scan

/*verilator coverage_on*/

input logic rst_l, // reset enable, from core pin

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode, // scan

/*verilator coverage_on*/

github-actions · 2024-10-16T10:24:53Z

design/lsu/el2_lsu_addrcheck.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.
+   /*verilator coverage_off*/
   input  logic         scan_mode                  // Scan mode
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode // Scan mode

/*verilator coverage_on*/

// Excluding scan_mode from coverage as its usage is determined by the integrator of VeeR the core.

/*verilator coverage_off*/

input logic scan_mode // Scan mode

/*verilator coverage_on*/

github-actions · 2024-10-16T12:28:43Z

design/dec/el2_dec_decode_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input  logic       scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

output logic [ 4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's

output logic dec_i0_wen_r, // i0 write enable

output logic [31:0] dec_i0_wdata_r, // i0 write data

github-actions · 2024-10-16T12:28:44Z

design/dec/el2_dec_gpr_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic        scan_mode
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

github-actions · 2024-10-16T12:28:44Z

design/dec/el2_dec_pmp_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input  logic        scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

github-actions · 2024-10-16T12:28:44Z

design/ifu/el2_ifu.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input logic scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

github-actions · 2024-10-16T12:28:44Z

design/ifu/el2_ifu_aln_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input logic                                    scan_mode,                // Flop scan mode control
+   /*verilator coverage_on*/
   input logic                                    rst_l,                    // reset, active low
   input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
   input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode, // Flop scan mode control

/*verilator coverage_on*/

input logic rst_l, // reset, active low

input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.

input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode, // Flop scan mode control

/*verilator coverage_on*/

input logic rst_l, // reset, active low

input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.

input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.

github-actions · 2024-10-16T12:28:44Z

design/ifu/el2_ifu_bp_ctl.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input  logic       scan_mode
+   /*verilator coverage_on*/
   );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode

/*verilator coverage_on*/

);

assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict

assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset

assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst

assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst

assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst

assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always

assign exu_mp_way = exu_mp_pkt.way; // repl way

assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history

assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0]; // target offset

assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address

assign exu_mp_ataken = exu_mp_pkt.ataken;

github-actions · 2024-10-16T12:28:45Z

design/ifu/el2_ifu_ifc_ctl.sv

   input logic rst_l, // reset enable, from core pin
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input logic scan_mode, // scan
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic rst_l, // reset enable, from core pin

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode, // scan

/*verilator coverage_on*/

input logic rst_l, // reset enable, from core pin

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode, // scan

/*verilator coverage_on*/

github-actions · 2024-10-16T12:28:45Z

design/lsu/el2_lsu_addrcheck.sv

+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
   input  logic         scan_mode                  // Scan mode
+   /*verilator coverage_on*/


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode // Scan mode

/*verilator coverage_on*/

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.

/*verilator coverage_off*/

input logic scan_mode // Scan mode

/*verilator coverage_on*/

github-actions · 2024-10-17T12:55:57Z

Links to coverage and verification reports for this PR (#247) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-11-08T17:44:58Z

Links to coverage and verification reports for this PR (#247) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

tmichalak · 2024-11-14T10:06:24Z

LGTM

github-actions bot reviewed Oct 15, 2024

View reviewed changes

wsipak force-pushed the wsip/exclude_scan_mode branch from 5f30409 to df12a72 Compare October 15, 2024 12:32

wsipak force-pushed the wsip/exclude_scan_mode branch 2 times, most recently from b58b03f to ae759de Compare October 16, 2024 07:49

wsipak force-pushed the wsip/exclude_scan_mode branch from ae759de to 4080d64 Compare October 16, 2024 10:23

github-actions bot reviewed Oct 16, 2024

View reviewed changes

wsipak force-pushed the wsip/exclude_scan_mode branch 2 times, most recently from 201eab7 to 3575fec Compare October 16, 2024 12:27

github-actions bot reviewed Oct 16, 2024

View reviewed changes

wsipak force-pushed the wsip/exclude_scan_mode branch 2 times, most recently from 99b9df9 to aee1480 Compare October 17, 2024 08:56

wsipak marked this pull request as ready for review October 17, 2024 13:10

wsipak added 2 commits November 8, 2024 15:58

exclude scan mode from coverage

2e280a8

exclude signals tied to const values from coverage

51d8b59

wsipak force-pushed the wsip/exclude_scan_mode branch from aee1480 to 51d8b59 Compare November 8, 2024 14:59

tmichalak merged commit aec88fc into main Nov 14, 2024
578 checks passed

wsipak deleted the wsip/exclude_scan_mode branch December 18, 2024 11:50

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Exclude signals tied to constant values #247

Exclude signals tied to constant values #247

wsipak commented Oct 15, 2024

github-actions bot Oct 15, 2024

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tmichalak commented Nov 14, 2024

		@@ -196,7 +196,10 @@ import el2_pkg::*;

		output logic dec_div_active, // non-block divide is active

	output logic dec_div_active, // non-block divide is active
	output logic dec_i0_alu_decode_d, // decode to D-stage alu
	output logic dec_i0_branch_d, // Branch in D-stage


	output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches

		@@ -39,7 +39,10 @@ import el2_pkg::*;
		output logic [31:0] rd0, // read data

		@@ -75,7 +75,10 @@ import el2_pkg::*;

		output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)

-   output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
+  logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
+  logic [1:0] bht_bank0_rd_data_f;
+  logic [1:0] bht_bank1_rd_data_f;
+  logic [1:0] bht_bank0_rd_data_p1_f;
+  genvar j, i;

-   /* exclude signals that are tied to constant value in tb_top.sv */
-   /*verilator coverage_off*/
-   input  logic       scan_mode
-   /*verilator coverage_on*/
-   );
+  assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f;  // conditional branch mispredict
+  assign exu_mp_boffset = exu_mp_pkt.boffset;  // branch offset
+  assign exu_mp_pc4 = exu_mp_pkt.pc4;  // branch is a 4B inst
+  assign exu_mp_call = exu_mp_pkt.pcall;  // branch is a call inst
+  assign exu_mp_ret = exu_mp_pkt.pret;  // branch is a ret inst
+  assign exu_mp_ja = exu_mp_pkt.pja;  // branch is a jump always
+  assign exu_mp_way = exu_mp_pkt.way;  // repl way
+  assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0];  // new history
+  assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0];  // target offset
+  assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ;  // BTB/BHT address
+  assign exu_mp_ataken = exu_mp_pkt.ataken;

		input logic ic_hit_f, // Icache hit
		input logic ifu_ic_mb_empty, // Miss buffer empty

Exclude signals tied to constant values #247

Exclude signals tied to constant values #247

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tmichalak commented Nov 14, 2024