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Parameter initialization with array assignment pattern containing default
produces invalid elaborated UHDM
#3803
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In this context But that's going to work only for elaborated data model : if BobaCount is override with a value different than 2 since systemVerilog data model does not record |
All the tests generate wrong UHDM. They all need to expand the const to 2^32-1 |
#3805 fixes the case: parameter int unsigned NumBobaDrinkers[BobaCount] = '{'1, '1} |
#3806 fixes the main case: parameter int unsigned NumBobaDrinkers[BobaCount] = '{default: '1} |
#3807 fixes parameter int unsigned NumBobaDrinkers[BobaCount] = '{BobaCount{'1}} |
There's still an empty typespec:
The "Similar test case that works (1)" has full typespec. |
It is not an empty typespec. In the case "that works", the typespec is cloned which makes it print in the -d uhdm, in the main case, it is not cloned, so the uhdm printer does not print it again, but it points to the correct typespec object. It is strictly the same. id:12 typespec in the elaborated tree points to the declaration in the non-elaborated tree with the same ID.
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@mglb can you confirm your are unblocked? |
Problematic test case
UHDM:
Issue: last constant and array_typespec are empty
Similar test case that works (1)
UHDM:
Similar test case that works (2)
UHDM:
Ref: chipsalliance/yosys-f4pga-plugins#539
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