FPGA Versal support for 2.0 #928
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Invalid workflow file:
.github/workflows/versioned-full-build-test.yml#L1
No steps defined in `steps` and no workflow called in `uses` for the following jobs: build-release, fpga-full-suite-etrng-log, fpga-full-suite-etrng-nolog, fpga-full-suite-itrng-log, fpga-full-suite-itrng-nolog, sw-emulator-full-suite-etrng-log, sw-emulator-full-suite-etrng-nolog, sw-emulator-full-suite-itrng-log, sw-emulator-full-suite-itrng-nolog
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