Elide metadata by default, add --include-util-metadata (#4475)

core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala

@@ -120,6 +120,7 @@ object Definition extends SourceInfoDoc {
         Nil,
         context.throwOnFirstError,
         context.useLegacyWidth,
+        context.includeUtilMetadata,
         context.warningFilters,
         context.sourceRoots,
         Some(context.globalNamespace),

core/src/main/scala/chisel3/internal/Builder.scala

@@ -473,12 +473,13 @@ private[chisel3] class ChiselContext() {
 }
 
 private[chisel3] class DynamicContext(
-  val annotationSeq:     AnnotationSeq,
-  val throwOnFirstError: Boolean,
-  val useLegacyWidth:    Boolean,
-  val warningFilters:    Seq[WarningFilter],
-  val sourceRoots:       Seq[File],
-  val defaultNamespace:  Option[Namespace],
+  val annotationSeq:       AnnotationSeq,
+  val throwOnFirstError:   Boolean,
+  val useLegacyWidth:      Boolean,
+  val includeUtilMetadata: Boolean,
+  val warningFilters:      Seq[WarningFilter],
+  val sourceRoots:         Seq[File],
+  val defaultNamespace:    Option[Namespace],
   // Definitions from other scopes in the same elaboration, use allDefinitions below
   val loggerOptions: LoggerOptions,
   val definitions:   ArrayBuffer[Definition[_]],
@@ -968,6 +969,8 @@ private[chisel3] object Builder extends LazyLogging {
 
   def useLegacyWidth: Boolean = dynamicContextVar.value.map(_.useLegacyWidth).getOrElse(false)
 
+  def includeUtilMetadata: Boolean = dynamicContextVar.value.map(_.includeUtilMetadata).getOrElse(false)
+
   // Builds a RenameMap for all Views that do not correspond to a single Data
   // These Data give a fake ReferenceTarget for .toTarget and .toReferenceTarget that the returned
   // RenameMap can split into the constituent parts

src/main/scala/chisel3/stage/ChiselAnnotations.scala

@@ -485,3 +485,21 @@ object RemapLayer extends HasShellOptions {
   )
 
 }
+
+/** Include metadata for chisel utils.
+  *
+  * Some built-in Chisel utilities (like [[chisel3.util.SRAM]]) can optionally be built with metadata.
+  * Adding this option will include the metadata when building relevant blocks.
+  *
+  * Use as CLI option `--include-util-metadata`.
+  */
+case object IncludeUtilMetadata extends NoTargetAnnotation with ChiselOption with HasShellOptions with Unserializable {
+
+  val options = Seq(
+    new ShellOption[Unit](
+      longOption = "include-util-metadata",
+      toAnnotationSeq = _ => Seq(IncludeUtilMetadata),
+      helpText = "Include metadata for chisel utils"
+    )
+  )
+}

src/main/scala/chisel3/stage/ChiselOptions.scala

@@ -15,7 +15,8 @@ class ChiselOptions private[stage] (
   val sourceRoots:         Vector[File] = Vector.empty,
   val warningFilters:      Vector[WarningFilter] = Vector.empty,
   val useLegacyWidth:      Boolean = false,
-  val layerMap:            Map[Layer, Layer] = Map.empty) {
+  val layerMap:            Map[Layer, Layer] = Map.empty,
+  val includeUtilMetadata: Boolean = false) {
 
   private[stage] def copy(
     printFullStackTrace: Boolean = printFullStackTrace,
@@ -25,7 +26,8 @@ class ChiselOptions private[stage] (
     sourceRoots:         Vector[File] = sourceRoots,
     warningFilters:      Vector[WarningFilter] = warningFilters,
     useLegacyWidth:      Boolean = useLegacyWidth,
-    layerMap:            Map[Layer, Layer] = layerMap
+    layerMap:            Map[Layer, Layer] = layerMap,
+    includeUtilMetadata: Boolean = includeUtilMetadata
   ): ChiselOptions = {
 
     new ChiselOptions(
@@ -36,7 +38,8 @@ class ChiselOptions private[stage] (
       sourceRoots = sourceRoots,
       warningFilters = warningFilters,
       useLegacyWidth = useLegacyWidth,
-      layerMap = layerMap
+      layerMap = layerMap,
+      includeUtilMetadata = includeUtilMetadata
     )
 
   }

src/main/scala/chisel3/stage/package.scala

@@ -31,6 +31,7 @@ package object stage {
           case a: WarningConfigurationFileAnnotation => c.copy(warningFilters = c.warningFilters ++ a.filters)
           case UseLegacyWidthBehavior         => c.copy(useLegacyWidth = true)
           case RemapLayer(oldLayer, newLayer) => c.copy(layerMap = c.layerMap + ((oldLayer, newLayer)))
+          case IncludeUtilMetadata            => c.copy(includeUtilMetadata = true)
         }
       }
 

src/main/scala/chisel3/stage/phases/Elaborate.scala

@@ -42,6 +42,7 @@ class Elaborate extends Phase {
             annotations,
             chiselOptions.throwOnFirstError,
             chiselOptions.useLegacyWidth,
+            chiselOptions.includeUtilMetadata,
             chiselOptions.warningFilters,
             chiselOptions.sourceRoots,
             None,

src/main/scala/chisel3/util/SRAM.scala

@@ -532,8 +532,11 @@ object SRAM {
     // underlying target
     val mem = autoNameRecursively("sram")(new SramTarget)
 
+    val includeMetadata = Builder.includeUtilMetadata
+
     // user-facing interface into the SRAM
-    val sramIntfType = new SRAMInterface(size, tpe, numReadPorts, numWritePorts, numReadwritePorts, isVecMem, true)
+    val sramIntfType =
+      new SRAMInterface(size, tpe, numReadPorts, numWritePorts, numReadwritePorts, isVecMem, includeMetadata)
     val _out = Wire(sramIntfType)
     _out._underlying = Some(HasTarget(mem))
 

src/test/scala/chiselTests/util/SRAMSpec.scala

@@ -5,6 +5,7 @@ package chiselTests.util
 import chisel3._
 import chisel3.util.{MemoryReadWritePort, SRAM}
 import chisel3.experimental.{annotate, ChiselAnnotation, OpaqueType}
+import chisel3.stage.IncludeUtilMetadata
 import chiselTests.ChiselFlatSpec
 import _root_.circt.stage.ChiselStage.{emitCHIRRTL, emitSystemVerilog}
 import firrtl.annotations.{Annotation, ReferenceTarget, SingleTargetAnnotation}
@@ -32,7 +33,7 @@ class SRAMSpec extends ChiselFlatSpec {
         override def toFirrtl: Annotation = DummyAnno(sram.underlying.get.toTarget)
       })
     }
-    val (chirrtlCircuit, annos) = getFirrtlAndAnnos(new Top)
+    val (chirrtlCircuit, annos) = getFirrtlAndAnnos(new Top, providedAnnotations = Seq(IncludeUtilMetadata))
     val chirrtl = chirrtlCircuit.serialize
     chirrtl should include("module Top :")
     chirrtl should include(
@@ -81,7 +82,7 @@ class SRAMSpec extends ChiselFlatSpec {
     chirrtl should include("module Top :")
     chirrtl should include("mem carrot :")
     chirrtl should include(
-      "wire sramInterface : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1], description : Inst<SRAMDescription>}"
+      "wire sramInterface : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}"
     )
 
     val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }
@@ -230,4 +231,22 @@ class SRAMSpec extends ChiselFlatSpec {
     // check CIRCT can compile the output
     val sv = emitSystemVerilog(new Top)
   }
+
+  it should "elide metadata by default" in {
+    class Top extends Module {
+      val sram = SRAM(
+        size = 32,
+        tpe = UInt(8.W),
+        numReadPorts = 0,
+        numWritePorts = 0,
+        numReadwritePorts = 1
+      )
+    }
+    val chirrtl = emitCHIRRTL(new Top)
+    // there should be no properties
+    chirrtl shouldNot include("class")
+    chirrtl shouldNot include("Integer")
+    chirrtl shouldNot include("Path")
+    chirrtl shouldNot include("propassign")
+  }
 }