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Original file line number | Diff line number | Diff line change |
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// SPDX-License-Identifier: Apache-2.0 | ||
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package chiselTests | ||
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import chisel3._ | ||
import circt.stage.ChiselStage | ||
import org.scalatest.matchers.should.Matchers | ||
import chiselTests.{ChiselFlatSpec, MatchesAndOmits} | ||
import chisel3.util.experimental.{InlineInstance, InlineInstanceAllowDedup} | ||
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class InlineInstanceSpec extends ChiselFlatSpec with MatchesAndOmits { | ||
class ModuleA extends RawModule { | ||
val w = dontTouch(WireInit(false.B)) | ||
} | ||
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class ModuleB extends RawModule with InlineInstance { | ||
val w = dontTouch(WireInit(false.B)) | ||
} | ||
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class TopModule extends RawModule { | ||
val a = Module(new ModuleA) | ||
val b = Module(new ModuleB) | ||
} | ||
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"InlineInstanceAllowDedup" should "Inline any module that dedups with a module marked inline" in { | ||
val verilog = ChiselStage.emitSystemVerilog(new TopModule) | ||
matchesAndOmits(verilog)( | ||
"module TopModule()", | ||
"module ModuleA();" | ||
)( | ||
"module ModuleB()" | ||
) | ||
} | ||
} | ||
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class InlineInstanceAllowDedupSpec extends ChiselFlatSpec with MatchesAndOmits { | ||
class ModuleA extends RawModule { | ||
val w = dontTouch(WireInit(false.B)) | ||
} | ||
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class ModuleB extends RawModule with InlineInstanceAllowDedup { | ||
val w = dontTouch(WireInit(false.B)) | ||
} | ||
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class TopModule extends RawModule { | ||
val a = Module(new ModuleA) | ||
val b = Module(new ModuleB) | ||
} | ||
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"InlineInstanceAllowDedup" should "Inline any module that dedups with a module marked inline" in { | ||
val verilog = ChiselStage.emitSystemVerilog(new TopModule) | ||
matchesAndOmits(verilog)( | ||
"module TopModule()" | ||
)( | ||
"module ModuleA()", | ||
"module ModuleB()" | ||
) | ||
} | ||
} |
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