-
Notifications
You must be signed in to change notification settings - Fork 600
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
feat: add CIRCTSRAMInterface #4494
Conversation
I like this API(since I originally designed it in our in-house codebase). Should it be In the future, I wanna it can provide additional port |
src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala
Outdated
Show resolved
Hide resolved
src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala
Outdated
Show resolved
Hide resolved
src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala
Outdated
Show resolved
Hide resolved
src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala
Outdated
Show resolved
Hide resolved
Signed-off-by: unlsycn <[email protected]>
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM
This PR provides a wrapper to generate a CIRCT-compatible SRAM, so that we can use it to replace the SRAM in the CIRCT.
Contributor Checklist
docs/src
?Type of Improvement
Desired Merge Strategy
Release Notes
Add CIRCTSRAMInterface
Reviewer Checklist (only modified by reviewer)
3.6.x
,5.x
, or6.x
depending on impact, API modification or big change:7.0
)?Enable auto-merge (squash)
, clean up the commit message, and label withPlease Merge
.Create a merge commit
.