Merge pull request #532 from antmicro/umarcor/docs/appendix

docs: add Appendix (Glossary and References)

docs/.gitignore

@@ -1,2 +1,3 @@
 /_build/
 /env/
+/status.inc

docs/community.rst

@@ -31,9 +31,9 @@ Communication
 Souces
 ======
 
-* `github.com/chipsalliance <https://github.com/chipsalliance/?q=f4pga>`__
+* :gh:`github.com/chipsalliance <chipsalliance/?q=f4pga>`
 
-* `github.com/F4PGA <https://github.com/F4PGA>`__
+* :gh:`github.com/F4PGA <F4PGA>`
 
 .. _Contributing:
 

docs/conf.py

@@ -43,10 +43,15 @@
 release = '' # The full version, including alpha/beta/rc tags.
 
 extensions = [
+    'sphinx.ext.extlinks',
     'sphinx.ext.intersphinx',
-    'sphinx_verilog_domain'
+    'sphinx_verilog_domain',
+    'sphinxcontrib.bibtex',
 ]
 
+bibtex_default_style = 'plain'
+bibtex_bibfiles = ['refs.bib']
+
 numfig = True
 
 templates_path = ['_templates']
@@ -140,3 +145,14 @@
     "prjxray": ("https://f4pga.readthedocs.io/projects/prjxray/en/latest/", None),
     "vtr": ("https://docs.verilogtorouting.org/en/latest/", None),
 }
+
+# -- Sphinx.Ext.ExtLinks -----------------------------------------------------------------------------------------------
+
+extlinks = {
+   'wikipedia': ('https://en.wikipedia.org/wiki/%s', 'wikipedia:'),
+   'gh':        ('https://github.com/%s', 'gh:'),
+   'ghsharp':   ('https://github.com/chipsalliance/f4pga/issues/%s', '#'),
+   'ghissue':   ('https://github.com/chipsalliance/f4pga/issues/%s', 'issue #'),
+   'ghpull':    ('https://github.com/chipsalliance/f4pga/pull/%s', 'pull request #'),
+   'ghsrc':     ('https://github.com/chipsalliance/f4pga/blob/master/%s', '')
+}