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Adjust Synlig to recent Yosys changes #2668

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Nov 22, 2024
Merged

Adjust Synlig to recent Yosys changes #2668

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9bd59a3
Adjust Synlig to Yosys internal API change
Szelwiga Oct 24, 2024
3a19d15
Add Yosys patches
Szelwiga Nov 8, 2024
071d737
Add alias write_ilang -> write_rtlil and update Yosys version
Szelwiga Nov 19, 2024
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3 changes: 2 additions & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -263,7 +263,8 @@ set(synlig_SRC
${PROJECT_SOURCE_DIR}/src/frontends/systemverilog/uhdm_common_frontend.cc
${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_const2ast.cc
${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_edif.cc
${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_simplify.cc)
${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_simplify.cc
${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_write_ilang.cc)

add_library(synlig SHARED ${synlig_SRC})

Expand Down
8 changes: 8 additions & 0 deletions Makefile
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Expand Up @@ -426,3 +426,11 @@ endef
$(foreach t,${GetTargetsList},$(foreach ts,$(call GetTargetStructName,${t}),$(eval $(value _single_target_rules))))

endif

#--------------------------------------------------------------------------------
# Add Yosys patches target

include ${TOP_DIR}/src/yosys_patches/Makefile.inc
build@synlig: apply_yosys_patches
build@yosys: apply_yosys_patches

2 changes: 1 addition & 1 deletion src/Makefile
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Expand Up @@ -18,7 +18,7 @@ CONFIG := none
# CONFIG := gcc

# --- add synlig cxxflags --- #
CXXFLAGS += -DSYNLIG_STANDALONE_BINARY -I $(SYNLIG_SRC)/frontends/*/ -I $(SYNLIG_SRC)/mods/* -I $(SYNLIG_SRC)/utils
CXXFLAGS += -DSYNLIG_STANDALONE_BINARY -I $(SYNLIG_SRC)/utils

# --- add static option --- #
CXXFLAGS += -static
Expand Down
3 changes: 2 additions & 1 deletion src/frontends/systemverilog/Build.mk
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Expand Up @@ -16,7 +16,8 @@ ${ts}.sources := \
${${ts}.src_dir}uhdm_surelog_ast_frontend.cc \
${${ts}.mod_dir}synlig_const2ast.cc \
${${ts}.mod_dir}synlig_edif.cc \
${${ts}.mod_dir}synlig_simplify.cc
${${ts}.mod_dir}synlig_simplify.cc \
${${ts}.mod_dir}synlig_write_ilang.cc

define ${ts}.env =
export PKG_CONFIG_PATH=$(call ShQuote,${$(call GetTargetStructName,surelog).output_vars.PKG_CONFIG_PATH}$(if ${PKG_CONFIG_PATH},:${PKG_CONFIG_PATH}))
Expand Down
2 changes: 2 additions & 0 deletions src/frontends/systemverilog/Makefile.inc
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@@ -1,4 +1,6 @@

CXXFLAGS += -I $(SYNLIG_SRC)/frontends/systemverilog

SYNLIG_OBJS += frontends/systemverilog/uhdm_ast.o
SYNLIG_OBJS += frontends/systemverilog/uhdm_ast_frontend.o
SYNLIG_OBJS += frontends/systemverilog/uhdm_common_frontend.o
Expand Down
3 changes: 3 additions & 0 deletions src/mods/yosys_ast/Makefile.inc
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@@ -1,4 +1,7 @@

CXXFLAGS += -I $(SYNLIG_SRC)/mods/yosys_ast

SYNLIG_OBJS += mods/yosys_ast/synlig_const2ast.o
SYNLIG_OBJS += mods/yosys_ast/synlig_edif.o
SYNLIG_OBJS += mods/yosys_ast/synlig_simplify.o
SYNLIG_OBJS += mods/yosys_ast/synlig_write_ilang.o
14 changes: 7 additions & 7 deletions src/mods/yosys_ast/synlig_edif.cc
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Expand Up @@ -321,24 +321,24 @@ struct SynligEdifBackend : public Backend {
auto add_prop = [&](IdString name, Const val) {
if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
else if (val.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
else {
std::string hex_string = "";
for (size_t i = 0; i < val.bits.size(); i += 4) {
for (size_t i = 0; i < val.size(); i += 4) {
int digit_value = 0;
if (i + 0 < val.bits.size() && val.bits.at(i + 0) == RTLIL::State::S1)
if (i + 0 < val.size() && val.at(i + 0) == RTLIL::State::S1)
digit_value |= 1;
if (i + 1 < val.bits.size() && val.bits.at(i + 1) == RTLIL::State::S1)
if (i + 1 < val.size() && val.at(i + 1) == RTLIL::State::S1)
digit_value |= 2;
if (i + 2 < val.bits.size() && val.bits.at(i + 2) == RTLIL::State::S1)
if (i + 2 < val.size() && val.at(i + 2) == RTLIL::State::S1)
digit_value |= 4;
if (i + 3 < val.bits.size() && val.bits.at(i + 3) == RTLIL::State::S1)
if (i + 3 < val.size() && val.at(i + 3) == RTLIL::State::S1)
digit_value |= 8;
char digit_str[2] = {"0123456789abcdef"[digit_value], 0};
hex_string = std::string(digit_str) + hex_string;
}
*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val), hex_string.c_str());
}
};
for (auto module : sorted_modules) {
Expand Down
52 changes: 26 additions & 26 deletions src/mods/yosys_ast/synlig_simplify.cc
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Expand Up @@ -1439,8 +1439,8 @@ bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zer
if (v->type == Yosys::AST::AST_CONSTANT && v->bits_only_01()) {
RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint);
RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1);
log_assert(match.bits.size() == 1);
if (match.bits.front() == RTLIL::State::S1) {
log_assert(match.size() == 1);
if (match.front() == RTLIL::State::S1) {
while (i + 1 < GetSize(ast_node->children))
delete ast_node->children[++i];
goto keep_const_cond;
Expand Down Expand Up @@ -1771,7 +1771,7 @@ bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zer
if (ast_node->children[1]->type != Yosys::AST::AST_CONSTANT)
log_file_error(ast_node->filename, ast_node->location.first_line, "Right operand of to_bits expression is not constant!\n");
RTLIL::Const new_value = ast_node->children[1]->bitsAsConst(ast_node->children[0]->bitsAsConst().as_int(), ast_node->children[1]->is_signed);
newNode = Yosys::AST::AstNode::mkconst_bits(new_value.bits, ast_node->children[1]->is_signed);
newNode = Yosys::AST::AstNode::mkconst_bits(new_value.to_bits(), ast_node->children[1]->is_signed);
goto apply_newNode;
}

Expand Down Expand Up @@ -1916,15 +1916,15 @@ bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zer
log_file_warning(ast_node->filename, ast_node->location.first_line, "converting real value %e to binary %s.\n",
ast_node->children[0]->realvalue, log_signal(constvalue));
delete ast_node->children[0];
ast_node->children[0] = Yosys::AST::AstNode::mkconst_bits(constvalue.bits, sign_hint);
ast_node->children[0] = Yosys::AST::AstNode::mkconst_bits(constvalue.to_bits(), sign_hint);
did_something = true;
}
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT) {
if (width != int(ast_node->children[0]->bits.size())) {
RTLIL::SigSpec sig(ast_node->children[0]->bits);
sig.extend_u0(width, ast_node->children[0]->is_signed);
Yosys::AST::AstNode *old_child_0 = ast_node->children[0];
ast_node->children[0] = Yosys::AST::AstNode::mkconst_bits(sig.as_const().bits, ast_node->is_signed);
ast_node->children[0] = Yosys::AST::AstNode::mkconst_bits(sig.as_const().to_bits(), ast_node->is_signed);
delete old_child_0;
}
ast_node->children[0]->is_signed = ast_node->is_signed;
Expand Down Expand Up @@ -3313,8 +3313,8 @@ skip_dynamic_range_lvalue_expansion:;
delete buf;

uint32_t result = 0;
for (size_t i = 0; i < arg_value.bits.size(); i++)
if (arg_value.bits.at(i) == RTLIL::State::S1)
for (size_t i = 0; i < arg_value.size(); i++)
if (arg_value.at(i) == RTLIL::State::S1)
result = i + 1;

newNode = ast_node->mkconst_int(result, true);
Expand Down Expand Up @@ -4111,14 +4111,14 @@ replace_fcall_later:;
case Yosys::AST::AST_BIT_NOT:
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = RTLIL::const_not(ast_node->children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), sign_hint);
}
break;
case Yosys::AST::AST_TO_SIGNED:
case Yosys::AST::AST_TO_UNSIGNED:
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = ast_node->children[0]->bitsAsConst(width_hint, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, ast_node->type == Yosys::AST::AST_TO_SIGNED);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), ast_node->type == Yosys::AST::AST_TO_SIGNED);
}
break;
if (0) {
Expand All @@ -4140,7 +4140,7 @@ replace_fcall_later:;
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT && ast_node->children[1]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = const_func(ast_node->children[0]->bitsAsConst(width_hint, sign_hint),
ast_node->children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), sign_hint);
}
break;
if (0) {
Expand All @@ -4165,14 +4165,14 @@ replace_fcall_later:;
}
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = const_func(RTLIL::Const(ast_node->children[0]->bits), dummy_arg, false, false, -1);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, false);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), false);
}
break;
case Yosys::AST::AST_LOGIC_NOT:
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y =
RTLIL::const_logic_not(RTLIL::Const(ast_node->children[0]->bits), dummy_arg, ast_node->children[0]->is_signed, false, -1);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, false);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), false);
} else if (ast_node->children[0]->isConst()) {
newNode = Yosys::AST::AstNode::mkconst_int(ast_node->children[0]->asReal(sign_hint) == 0, false, 1);
}
Expand All @@ -4188,7 +4188,7 @@ replace_fcall_later:;
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT && ast_node->children[1]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = const_func(RTLIL::Const(ast_node->children[0]->bits), RTLIL::Const(ast_node->children[1]->bits),
ast_node->children[0]->is_signed, ast_node->children[1]->is_signed, -1);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, false);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), false);
} else if (ast_node->children[0]->isConst() && ast_node->children[1]->isConst()) {
if (ast_node->type == Yosys::AST::AST_LOGIC_AND)
newNode = Yosys::AST::AstNode::mkconst_int(
Expand Down Expand Up @@ -4221,7 +4221,7 @@ replace_fcall_later:;
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT && ast_node->children[1]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = const_func(ast_node->children[0]->bitsAsConst(width_hint, sign_hint), RTLIL::Const(ast_node->children[1]->bits),
sign_hint, ast_node->type == Yosys::AST::AST_POW ? ast_node->children[1]->is_signed : false, width_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), sign_hint);
} else if (ast_node->type == Yosys::AST::AST_POW && ast_node->children[0]->isConst() && ast_node->children[1]->isConst()) {
newNode = new Yosys::AST::AstNode(Yosys::AST::AST_REALVALUE);
newNode->realvalue = pow(ast_node->children[0]->asReal(sign_hint), ast_node->children[1]->asReal(sign_hint));
Expand Down Expand Up @@ -4264,7 +4264,7 @@ replace_fcall_later:;
bool cmp_signed = ast_node->children[0]->is_signed && ast_node->children[1]->is_signed;
RTLIL::Const y = const_func(ast_node->children[0]->bitsAsConst(cmp_width, cmp_signed),
ast_node->children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, false);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), false);
} else if (ast_node->children[0]->isConst() && ast_node->children[1]->isConst()) {
bool cmp_signed = (ast_node->children[0]->type == Yosys::AST::AST_REALVALUE || ast_node->children[0]->is_signed) &&
(ast_node->children[1]->type == Yosys::AST::AST_REALVALUE || ast_node->children[1]->is_signed);
Expand Down Expand Up @@ -4329,7 +4329,7 @@ replace_fcall_later:;
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT && ast_node->children[1]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = const_func(ast_node->children[0]->bitsAsConst(width_hint, sign_hint),
ast_node->children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), sign_hint);
} else if (ast_node->children[0]->isConst() && ast_node->children[1]->isConst()) {
newNode = new Yosys::AST::AstNode(Yosys::AST::AST_REALVALUE);
switch (ast_node->type) {
Expand Down Expand Up @@ -4367,7 +4367,7 @@ replace_fcall_later:;
}
if (ast_node->children[0]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const y = const_func(ast_node->children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), sign_hint);
} else if (ast_node->children[0]->isConst()) {
newNode = new Yosys::AST::AstNode(Yosys::AST::AST_REALVALUE);
if (ast_node->type == Yosys::AST::AST_NEG)
Expand All @@ -4393,22 +4393,22 @@ replace_fcall_later:;
newNode->realvalue = choice->asReal(sign_hint);
} else {
RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint);
if (choice->is_string && y.bits.size() % 8 == 0 && sign_hint == false)
newNode = Yosys::AST::AstNode::mkconst_str(y.bits);
if (choice->is_string && y.size() % 8 == 0 && sign_hint == false)
newNode = Yosys::AST::AstNode::mkconst_str(y.to_bits());
else
newNode = Yosys::AST::AstNode::mkconst_bits(y.bits, sign_hint);
newNode = Yosys::AST::AstNode::mkconst_bits(y.to_bits(), sign_hint);
}
} else if (choice->isConst()) {
newNode = choice->clone();
}
} else if (ast_node->children[1]->type == Yosys::AST::AST_CONSTANT && ast_node->children[2]->type == Yosys::AST::AST_CONSTANT) {
RTLIL::Const a = ast_node->children[1]->bitsAsConst(width_hint, sign_hint);
RTLIL::Const b = ast_node->children[2]->bitsAsConst(width_hint, sign_hint);
log_assert(a.bits.size() == b.bits.size());
for (size_t i = 0; i < a.bits.size(); i++)
if (a.bits[i] != b.bits[i])
a.bits[i] = RTLIL::State::Sx;
newNode = Yosys::AST::AstNode::mkconst_bits(a.bits, sign_hint);
log_assert(a.size() == b.size());
for (size_t i = 0; i < a.size(); i++)
if (a[i] != b[i])
a.bits()[i] = RTLIL::State::Sx;
newNode = Yosys::AST::AstNode::mkconst_bits(a.to_bits(), sign_hint);
} else if (ast_node->children[1]->isConst() && ast_node->children[2]->isConst()) {
newNode = new Yosys::AST::AstNode(Yosys::AST::AST_REALVALUE);
if (ast_node->children[1]->asReal(sign_hint) == ast_node->children[2]->asReal(sign_hint))
Expand All @@ -4429,7 +4429,7 @@ replace_fcall_later:;
val = ast_node->children[1]->bitsAsUnsizedConst(width);
else
val = ast_node->children[1]->bitsAsConst(width);
newNode = Yosys::AST::AstNode::mkconst_bits(val.bits, ast_node->children[1]->is_signed);
newNode = Yosys::AST::AstNode::mkconst_bits(val.to_bits(), ast_node->children[1]->is_signed);
}
break;
case Yosys::AST::AST_CONCAT:
Expand Down
24 changes: 24 additions & 0 deletions src/mods/yosys_ast/synlig_write_ilang.cc
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@@ -0,0 +1,24 @@
#include "kernel/yosys.h"

namespace Synlig
{

using namespace ::Yosys;
struct WriteIlangAlias : public Pass {
WriteIlangAlias() : Pass("write_ilang", "alias for write_rtlil pass") {}
void help() override
{
log_warning("write_ilang pass is an alias for write_rtlil pass.\n\n");
run_pass("help write_rtlil");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_warning("write_ilang pass is an alias for write_rtlil pass.\n\n");
std::string cmd = "write_rtlil";
for (int i = 1; i < args.size(); i++)
cmd += " " + args[i];
run_pass(cmd, design);
}
} WriteIlangAliasPass;

} // namespace Synlig
25 changes: 25 additions & 0 deletions src/yosys_patches/0001-Fix-setting-undef-bits-in-parameters.patch
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@@ -0,0 +1,25 @@
From 84a9827ed92421008542a7d85e9381607b9add7b Mon Sep 17 00:00:00 2001
From: mszelwiga <[email protected]>
Date: Thu, 21 Nov 2024 14:26:39 +0100
Subject: [PATCH] Fix setting undef bits in parameters

---
passes/cmds/setundef.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 4ba58036b..dce33c05b 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
- for (auto bit : parameter.second) {
+ for (auto &bit : parameter.second.bits()) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}
--
2.39.2

6 changes: 6 additions & 0 deletions src/yosys_patches/Makefile.inc
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@@ -0,0 +1,6 @@
SYNLIG_SRC ?= $(TOP_DIR)/src
YOSYS_SRC ?= $(TOP_DIR)/third_party/yosys
PATCHES_DIR := $(SYNLIG_SRC)/yosys_patches

apply_yosys_patches:
if ! (cd $(YOSYS_SRC) && git apply --reverse --check $(PATCHES_DIR)/*.patch 2> /dev/null); then (cd $(YOSYS_SRC) && git apply $(PATCHES_DIR)/*.patch); fi
5 changes: 3 additions & 2 deletions tests/formal/testlist.json
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,8 @@
},
"unstable": {
"sv2v": [
"core/for_decl.v"
"core/for_decl.v",
"core/named_block.v"
]
},
"multiple topmodules": {
Expand Down Expand Up @@ -459,6 +460,7 @@
"sim/sdff.v",
"sim/sdffce.v",
"sim/sdffe.v",
"sim/simple_assign.v",
"simple/aes_kexp128.v",
"simple/always01.v",
"simple/always02.v",
Expand Down Expand Up @@ -1117,7 +1119,6 @@
"core/multipack_port.v",
"core/multipack_struct_cast.sv",
"core/multipack_tb.v",
"core/named_block.v",
"core/named_genblk_cascade_tb.v",
"core/no_default_param.sv",
"core/non_ansi_port_decl_order_tb.v",
Expand Down
2 changes: 1 addition & 1 deletion third_party/yosys
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Submodule yosys updated 255 files
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