[t1rocket] fix the repeatition with regwrite and checkRd

t1rocketemu/offline/src/difftest.rs

@@ -39,10 +39,10 @@ impl Difftest {
         Ok(())
       }
       JsonEvents::SimulationStop { reason, cycle } => {
-        anyhow::bail!("error: simulation stopped at cycle {}, reason {}", cycle, reason)
+        anyhow::bail!("error: simulation stopped at cycle {cycle}, reason {reason}")
       }
       JsonEvents::SimulationEnd { cycle } => {
-        anyhow::bail!("simulation quit successfullly cycle {}", cycle);
+        anyhow::bail!("simulation quit successfullly cycle {cycle}");
       }
       JsonEvents::RegWrite { idx, data, cycle } => {
         self.runner.cycle = *cycle;

t1rocketemu/offline/src/dut.rs

@@ -41,7 +41,17 @@ impl Dut {
       Some(event) => event,
       None => anyhow::bail!("error: simulation stopped with no more events"),
     };
-    self.idx += 1;
+
+    // skip the next event with vector reg write
+    // TODO: fix this in rtl
+    match event {
+      JsonEvents::CheckRd { .. } => {
+        self.idx += 2;
+      }
+      _ => {
+        self.idx += 1;
+      }
+    }
 
     Ok(event)
   }

t1rocketemu/offline/src/json_events.rs

@@ -178,14 +178,22 @@ impl JsonEventRunner for SpikeRunner {
     let se = self.find_rf_se();
 
     info!(
-      "[{cycle}] RegWrite: rtl idx={idx}, data={data:08x}; se idx={}, data={:08x} ({})",
+      "[{cycle}] RegWrite: rtl idx={idx}, data={data:#08x}; se idx={}, data={:#08x} ({})",
       se.rd_idx,
       se.rd_bits,
       se.describe_insn()
     );
 
-    assert!(idx as u32 == se.rd_idx, "rtl idx({:#x}) should be equal to spike idx({:#x})", idx, se.rd_idx);
-    assert!(data == se.rd_bits, "rtl data({:#x}) should be equal to spike data({:#x})", data, se.rd_bits);
+    assert!(
+      idx as u32 == se.rd_idx,
+      "rtl idx({idx:#x}) should be equal to spike idx({:#x})",
+      se.rd_idx
+    );
+    assert!(
+      data == se.rd_bits,
+      "rtl data({data:#x}) should be equal to spike data({:#x})",
+      se.rd_bits
+    );
 
     Ok(())
   }
@@ -274,7 +282,7 @@ impl JsonEventRunner for SpikeRunner {
           assert_eq!(
             record.byte,
             written_byte,
-            "[{}] {offset}th byte incorrect ({:02x} record != {written_byte:02x} written) \
+            "[{}] {offset}th byte incorrect ({:#02x} record != {written_byte:#02x} written) \
               for vrf write (lane={}, vd={}, offset={}, mask={}, data={:x?}) \
               issue_idx={} [vrf_idx={}] (disasm: {}, pc: {:#x}, bits: {:#x})",
             vrf_write.cycle,
@@ -328,7 +336,7 @@ impl JsonEventRunner for SpikeRunner {
     let lsu_idx = memory_write.lsu_idx;
 
     if let Some(se) = self.commit_queue.iter_mut().find(|se| se.lsu_idx == lsu_idx) {
-      info!("[{cycle}] MemoryWrite: address={base_addr:08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm);
+      info!("[{cycle}] MemoryWrite: address={base_addr:#08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm);
       // compare with spike event record
       mask.iter().enumerate()
         .filter(|(_, &mask)| mask)
@@ -337,11 +345,11 @@ impl JsonEventRunner for SpikeRunner {
           let data_byte = *data.get(offset).unwrap_or(&0);
           let mem_write =
             se.mem_access_record.all_writes.get_mut(&byte_addr).unwrap_or_else(|| {
-              panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:08x}")
+              panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:#08x}")
             });
           let single_mem_write_val = mem_write.writes[mem_write.num_completed_writes].val;
           mem_write.num_completed_writes += 1;
-          assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:02X}, actual byte {data_byte:02X} (byte_addr={byte_addr:08X}, pc = {:#x}, disasm = {})", se.pc, se.disasm);
+          assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:#02x}, actual byte {data_byte:#02x} (byte_addr={byte_addr:#08x}, pc = {:#x}, disasm = {})", se.pc, se.disasm);
         });
       return Ok(());
     }

t1rocketemu/spike_rs/src/spike_event.rs

@@ -325,18 +325,15 @@ impl SpikeEvent {
 
   pub fn pre_log_arch_changes(&mut self, spike: &Spike, vlen: u32) -> anyhow::Result<()> {
     if self.do_log_vrf {
-      self.rd_bits = spike.get_proc().get_rd();
-
       // record the vrf writes before executing the insn
-      let vlen_in_bytes = vlen;
-
       let proc = spike.get_proc();
-      let (start, len) = self.get_vrf_write_range(vlen_in_bytes).unwrap();
+      self.rd_bits = proc.get_state().get_reg(self.rd_idx, false);
+      let (start, len) = self.get_vrf_write_range(vlen).unwrap();
       self.vd_write_record.vd_bytes.resize(len as usize, 0u8);
       for i in 0..len {
         let offset = start + i;
-        let vreg_index = offset / vlen_in_bytes;
-        let vreg_offset = offset % vlen_in_bytes;
+        let vreg_index = offset / vlen;
+        let vreg_offset = offset % vlen;
         let cur_byte = proc.get_vreg_data(vreg_index, vreg_offset);
         self.vd_write_record.vd_bytes[i as usize] = cur_byte;
       }
@@ -412,7 +409,7 @@ impl SpikeEvent {
             self.is_rd_written = true;
             self.rd_bits = data;
             trace!(
-              "ScalarRFChange: idx={:02x}, data={:08x}",
+              "ScalarRFChange: idx={:#02x}, data={:08x}",
               self.rd_idx,
               self.rd_bits
             );
@@ -424,13 +421,13 @@ impl SpikeEvent {
           self.is_rd_written = true;
           self.rd_bits = data;
           trace!(
-            "FloatRFChange: idx={:02x}, data={:08x}",
+            "FloatRFChange: idx={:#02x}, data={:08x}",
             self.rd_idx,
             self.rd_bits
           );
         }
         _ => trace!(
-          "UnknownRegChange, idx={:02x}, spike detect unknown reg change",
+          "UnknownRegChange, idx={:#02x}, spike detect unknown reg change",
           self.rd_idx
         ),
       }