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[rtl] remove duplicated names
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@sequencer
sequencer committed Apr 20, 2024
1 parent b2db039 commit f66b919
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Showing 2 changed files with 44 additions and 32 deletions.
69 changes: 37 additions & 32 deletions t1/src/Lane.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -533,8 +533,13 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
val stage0: Instance[LaneStage0] = Instantiate(new LaneStage0(parameter, isLastSlot))
val stage1: Instance[LaneStage1] = Instantiate(new LaneStage1(parameter, isLastSlot))
val stage2: Instance[LaneStage2] = Instantiate(new LaneStage2(parameter, isLastSlot))
val executionUnit: Instance[LaneExecutionBridge] = Instantiate(new LaneExecutionBridge(parameter, isLastSlot, index))
val executionBridge: Instance[LaneExecutionBridge] = Instantiate(new LaneExecutionBridge(parameter, isLastSlot, index))
val stage3: Instance[LaneStage3] = Instantiate(new LaneStage3(parameter, isLastSlot))
stage0.suggestName(s"slot${index}Stage0")
stage1.suggestName(s"slot${index}Stage1")
stage2.suggestName(s"slot${index}Stage2")
stage3.suggestName(s"slot${index}Stage3")
executionBridge.suggestName(s"slot${index}LaneExecutionBridge")

// slot state
laneState.vSew1H := vSew1H
Expand Down Expand Up @@ -670,9 +675,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
indexToOH(record.laneRequest.instructionIndex, parameter.chainingSize)
)

stage2.enqueue.valid := stage1.dequeue.valid && executionUnit.enqueue.ready
stage1.dequeue.ready := stage2.enqueue.ready && executionUnit.enqueue.ready
executionUnit.enqueue.valid := stage1.dequeue.valid && stage2.enqueue.ready
stage2.enqueue.valid := stage1.dequeue.valid && executionBridge.enqueue.ready
stage1.dequeue.ready := stage2.enqueue.ready && executionBridge.enqueue.ready
executionBridge.enqueue.valid := stage1.dequeue.valid && stage2.enqueue.ready

stage2.state := laneState
stage2.enqueue.bits.groupCounter := stage1.dequeue.bits.groupCounter
Expand All @@ -682,35 +687,35 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
stage2.enqueue.bits.sSendResponse.zip(stage1.dequeue.bits.sSendResponse).foreach { case (sink, source) =>
sink := source
}
stage2.enqueue.bits.bordersForMaskLogic := executionUnit.enqueue.bits.bordersForMaskLogic
stage2.enqueue.bits.bordersForMaskLogic := executionBridge.enqueue.bits.bordersForMaskLogic

executionUnit.state := laneState
executionUnit.enqueue.bits.src := stage1.dequeue.bits.src
executionUnit.enqueue.bits.bordersForMaskLogic :=
executionBridge.state := laneState
executionBridge.enqueue.bits.src := stage1.dequeue.bits.src
executionBridge.enqueue.bits.bordersForMaskLogic :=
(stage1.dequeue.bits.groupCounter === record.lastGroupForInstruction && record.isLastLaneForInstruction)
executionUnit.enqueue.bits.mask := stage1.dequeue.bits.mask
executionUnit.enqueue.bits.maskForFilter := stage1.dequeue.bits.maskForFilter
executionUnit.enqueue.bits.groupCounter := stage1.dequeue.bits.groupCounter
executionUnit.enqueue.bits.sSendResponse.zip(stage1.dequeue.bits.sSendResponse).foreach { case (sink, source) =>
executionBridge.enqueue.bits.mask := stage1.dequeue.bits.mask
executionBridge.enqueue.bits.maskForFilter := stage1.dequeue.bits.maskForFilter
executionBridge.enqueue.bits.groupCounter := stage1.dequeue.bits.groupCounter
executionBridge.enqueue.bits.sSendResponse.zip(stage1.dequeue.bits.sSendResponse).foreach { case (sink, source) =>
sink := source
}
executionUnit.enqueue.bits.crossReadSource.zip(stage1.dequeue.bits.crossReadSource).foreach { case (sink, source) =>
executionBridge.enqueue.bits.crossReadSource.zip(stage1.dequeue.bits.crossReadSource).foreach { case (sink, source) =>
sink := source
}

executionUnit.ffoByOtherLanes := record.ffoByOtherLanes
executionUnit.selfCompleted := record.selfCompleted
executionBridge.ffoByOtherLanes := record.ffoByOtherLanes
executionBridge.selfCompleted := record.selfCompleted

// executionUnit <> vfu
requestVec(index) := executionUnit.vfuRequest.bits
executeEnqueueValid(index) := executionUnit.vfuRequest.valid
executionUnit.vfuRequest.ready := executeEnqueueFire(index)
executionUnit.dataResponse := responseVec(index)
requestVec(index) := executionBridge.vfuRequest.bits
executeEnqueueValid(index) := executionBridge.vfuRequest.valid
executionBridge.vfuRequest.ready := executeEnqueueFire(index)
executionBridge.dataResponse := responseVec(index)

when(executionUnit.dequeue.valid)(assert(stage2.dequeue.valid))
stage3.enqueue.valid := executionUnit.dequeue.valid
executionUnit.dequeue.ready := stage3.enqueue.ready
stage2.dequeue.ready := executionUnit.dequeue.fire
when(executionBridge.dequeue.valid)(assert(stage2.dequeue.valid))
stage3.enqueue.valid := executionBridge.dequeue.valid
executionBridge.dequeue.ready := stage3.enqueue.ready
stage2.dequeue.ready := executionBridge.dequeue.fire

if (!isLastSlot) {
stage3.enqueue.bits := DontCare
Expand All @@ -720,17 +725,17 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
stage3.enqueue.bits.mask := stage2.dequeue.bits.mask
if (isLastSlot) {
stage3.enqueue.bits.sSendResponse := stage2.dequeue.bits.sSendResponse.get
stage3.enqueue.bits.ffoSuccess := executionUnit.dequeue.bits.ffoSuccess.get
stage3.enqueue.bits.fpReduceValid.zip(executionUnit.dequeue.bits.fpReduceValid).foreach {
stage3.enqueue.bits.ffoSuccess := executionBridge.dequeue.bits.ffoSuccess.get
stage3.enqueue.bits.fpReduceValid.zip(executionBridge.dequeue.bits.fpReduceValid).foreach {
case (sink, source) => sink := source
}
}
stage3.enqueue.bits.data := executionUnit.dequeue.bits.data
stage3.enqueue.bits.data := executionBridge.dequeue.bits.data
stage3.enqueue.bits.pipeData := stage2.dequeue.bits.pipeData.getOrElse(DontCare)
stage3.enqueue.bits.ffoIndex := executionUnit.dequeue.bits.ffoIndex
executionUnit.dequeue.bits.crossWriteData.foreach(data => stage3.enqueue.bits.crossWriteData := data)
stage3.enqueue.bits.ffoIndex := executionBridge.dequeue.bits.ffoIndex
executionBridge.dequeue.bits.crossWriteData.foreach(data => stage3.enqueue.bits.crossWriteData := data)
stage2.dequeue.bits.sSendResponse.foreach(_ => stage3.enqueue.bits.sSendResponse := _)
executionUnit.dequeue.bits.ffoSuccess.foreach(_ => stage3.enqueue.bits.ffoSuccess := _)
executionBridge.dequeue.bits.ffoSuccess.foreach(_ => stage3.enqueue.bits.ffoSuccess := _)

if (isLastSlot){
when(laneResponseFeedback.valid && slotOccupied(index)) {
Expand All @@ -739,7 +744,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
}
}
when(stage3.enqueue.fire) {
executionUnit.dequeue.bits.ffoSuccess.foreach(record.selfCompleted := _)
executionBridge.dequeue.bits.ffoSuccess.foreach(record.selfCompleted := _)
// This group found means the next group ended early
record.ffoByOtherLanes := record.ffoByOtherLanes || record.selfCompleted
}
Expand All @@ -766,8 +771,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
probeWire.slots(index).slotShiftValid := slotShiftValid(index)
probeWire.slots(index).decodeResultIsCrossReadOrWrite := decodeResult(Decoder.crossRead) || decodeResult(Decoder.crossWrite)
probeWire.slots(index).decodeResultIsScheduler := decodeResult(Decoder.scheduler)
probeWire.slots(index).executionUnitVfuRequestReady := executionUnit.vfuRequest.ready
probeWire.slots(index).executionUnitVfuRequestValid := executionUnit.vfuRequest.valid
probeWire.slots(index).executionUnitVfuRequestReady := executionBridge.vfuRequest.ready
probeWire.slots(index).executionUnitVfuRequestValid := executionBridge.vfuRequest.valid
probeWire.slots(index).stage3VrfWriteReady := stage3.vrfWriteRequest.ready
probeWire.slots(index).stage3VrfWriteValid := stage3.vrfWriteRequest.valid
// probeWire.slots(index).probeStage1 := ???
Expand Down
7 changes: 7 additions & 0 deletions t1/src/T1.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -279,7 +279,9 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
/** the LSU Module */

val lsu: Instance[LSU] = Instantiate(new LSU(parameter.lsuParameters))
lsu.suggestName("lsu")
val decode: Instance[VectorDecoder] = Instantiate(new VectorDecoder(parameter.fpuEnable))
decode.suggestName("decoder")

// TODO: cover overflow
// TODO: uarch doc about the order of instructions
Expand Down Expand Up @@ -827,10 +829,14 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
val skipFlotReduce: Bool = !Mux1H(UIntToOH(executeCounter), flotReduceValid.map(_.getOrElse(false.B)))
// red alu instance
val adder: Instance[ReduceAdder] = Instantiate(new ReduceAdder(parameter.datapathWidth))
adder.suggestName(s"slot${index}ReduceAdder")
val logicUnit: Instance[LaneLogic] = Instantiate(new LaneLogic(parameter.datapathWidth))
logicUnit.suggestName(s"slot${index}LogicUnit")
// option unit for flot reduce
val floatAdder: Option[Instance[FloatAdder]] = Option.when(parameter.fpuEnable)(Instantiate(new FloatAdder(8, 24)))
floatAdder.foreach(_.suggestName(s"slot${index}floatAdder"))
val flotCompare: Option[Instance[FloatCompare]] = Option.when(parameter.fpuEnable)(Instantiate(new FloatCompare(8, 24)))
floatAdder.foreach(_.suggestName(s"slot${index}flotCompare"))

val sign = !decodeResultReg(Decoder.unsigned1)
adder.request.src := VecInit(
Expand Down Expand Up @@ -1376,6 +1382,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
*/
val laneVec: Seq[Instance[Lane]] = Seq.tabulate(parameter.laneNumber) { index =>
val lane: Instance[Lane] = Instantiate(new Lane(parameter.laneParam))
lane.suggestName(s"lane$index")
// lane.laneRequest.valid -> requestRegDequeue.ready -> lane.laneRequest.ready -> lane.laneRequest.bits
// TODO: this is harmful for PnR design, since it broadcast ready singal to each lanes, which will significantly
// reduce the scalability for large number of lanes.
Expand Down

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