Jiuyang/rocket t1 #715
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Jiuyang/rocket t1 #715
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- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ALU config --xLen 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ALU design --parameter ./ALU.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.AMOALU config --operandBits 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.AMOALU design --parameter ./AMOALU.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BreakpointUnit config --nBreakpoints 4 --xLen 32 --useBPWatch true --vaddrBits 32 --mcontextWidth 0 --scontextWidth 0 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BreakpointUnit design --parameter ./BreakpointUnit.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BTB config --useAsyncReset true --fetchBytes 16 --vaddrBits 34 --entries 28 --nMatchBits 14 --nPages 6 --nRAS 6 --cacheBlockBytes 64 --iCacheSet 64 --useCompressed true --updatesOutOfOrder false --bht-nEntries 512 --bht-counterLength 1 --bht-historyLength 8 --bht-historyBits 3 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BTB design --parameter ./BTB.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.CSR config --vLen 512 --useAsyncReset false --xLen 32 --fLen 32 --usingSupervisor false --usingFPU true --usingUser false --usingVM false --pgLevels 2 --hartIdLen 1 --usingCompressed true --usingAtomics true --usingDebug true --usingMulDiv true --usingVector true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.CSR design --parameter ./CSR.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Decoder config --pipelinedMul false --fenceIFlushDCache false --instructionSets rv32_i --instructionSets rv_v - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Decoder design --parameter ./Decoder.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RVCExpander config --xLen 32 --usingCompressed true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RVCExpander design --parameter ./RVCExpander.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.IBuf design --useAsyncReset true --xLen 32 --usingCompressed true --vaddrBits 32 --entries 4 --vaddrBitsExtended 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.IBuf design --parameter ./IBuf.json --run-firtool
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile config --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile design --parameter ./T1RocketTile.json --run-firtool
nix develop ".#t1.elaborator.editable" -c mill -i elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile config --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --instructionSets rv_c
…d resetVector retrieval
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
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Close in favor of #717 . |
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