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Add OM for VRF #721

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Add OM for VRF #721

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6 changes: 6 additions & 0 deletions t1/src/Lane.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,11 @@ class LaneOM extends Class {
@public
val vfusIn = IO(Input(Property[Seq[AnyClassType]]()))
vfus := vfusIn
@public
val vrf = IO(Output(Property[AnyClassType]()))
@public
val vrfIn = IO(Input(Property[AnyClassType]()))
vrf := vrfIn
}

class LaneSlotProbe(instructionIndexBits: Int) extends Bundle {
Expand Down Expand Up @@ -325,6 +330,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[

/** VRF instantces. */
val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam))
omInstance.vrfIn := Property(vrf.om.asAnyClassType)

/** TODO: review later
*/
Expand Down
19 changes: 18 additions & 1 deletion t1/src/vrf/VRF.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,10 @@
package org.chipsalliance.t1.rtl.vrf

import chisel3._
import chisel3.experimental.hierarchy.{Instantiate, instantiable, public}
import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable, public}
import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
import chisel3.probe.{Probe, ProbeValue, define}
import chisel3.properties.{AnyClassType, Class, ClassType, Property}
import chisel3.util._
import org.chipsalliance.t1.rtl.{LSUWriteCheck, VRFReadPipe, VRFReadRequest, VRFWriteReport, VRFWriteRequest, ffo, instIndexL, instIndexLE, ohCheck}

Expand All @@ -28,6 +29,16 @@ object VRFParam {
implicit val rwP: upickle.default.ReadWriter[VRFParam] = upickle.default.macroRW
}


@instantiable
class VRFOM extends Class {
@public
val vrfSRAMOM = IO(Output(Property[Seq[AnyClassType]]()))
@public
val vrfSRAMOMIn = IO(Input(Property[Seq[AnyClassType]]()))
vrfSRAMOM := vrfSRAMOMIn
}

/** Parameter for [[Lane]].
* @param vLen VLEN
* @param laneNumber how many lanes in the vector processor
Expand Down Expand Up @@ -127,6 +138,11 @@ class VRFProbe(parameter: VRFParam) extends Bundle {
*/
@instantiable
class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFParam] {
val omInstance: Instance[VRFOM] = Instantiate(new VRFOM)
val omType: ClassType = omInstance.toDefinition.getClassType
@public
val om: Property[ClassType] = IO(Output(Property[omType.Type]()))
om := omInstance.getPropertyReference

/** VRF read requests
* ready will couple from valid from [[readRequests]],
Expand Down Expand Up @@ -434,6 +450,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar

rf
}
omInstance.vrfSRAMOMIn := Property(rfVec.map(_.description.asAnyClassType))

val initRecord: ValidIO[VRFWriteReport] = WireDefault(0.U.asTypeOf(Valid(new VRFWriteReport(parameter))))
initRecord.valid := true.B
Expand Down
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