Debugging of gbtx link

src/gbt/gbt_rx.vhd

@@ -70,8 +70,13 @@ architecture Behavioral of gbt_rx is
 
     signal sync_valid : boolean;
     signal idle_valid : boolean;
+    signal busy       : boolean;
 
     signal reset : std_logic;
+    signal l1a           : std_logic;
+    signal bc0           : std_logic;
+    signal resync        : std_logic;
+    signal reset_vfats   : std_logic;
 
 begin
 
@@ -114,18 +119,17 @@ begin
                 resync_o <= '0';
                 bc0_o    <= '0';
             else
-                case state is
-                    when SYNCING =>
+                if ( idle_valid or sync_valid or busy=True ) then
+                        l1a_o         <= l1a;
+                        reset_vfats_o <= reset_vfats;
+                        resync_o      <= resync;
+                        bc0_o         <= bc0;
+                else
                         l1a_o         <= '0';
                         reset_vfats_o <= '0';
                         resync_o      <= '0';
                         bc0_o         <= '0';
-                    when others  =>
-                        l1a_o         <= data_i(15);
-                        reset_vfats_o <= data_i(14);
-                        resync_o      <= data_i(13);
-                        bc0_o         <= data_i(12);
-                end case;
+                end if;
             end if;
         end if;
     end process;
@@ -144,7 +148,11 @@ begin
 
     g_ten : IF (not g_16BIT) GENERATE
 
-    data6 <= data_i (11 downto 8) & data_i (6) & data_i(2);
+    l1a         <= data_i (15);
+    reset_vfats <= data_i (14);
+    resync      <= data_i (13);
+    bc0         <= data_i (12);
+    data6       <= data_i (11 downto 8) & data_i (5) & data_i (1);
 
     sync_valid <= (data6 = "101010"); -- use a 6 bit end frame symbol
     idle_valid <= (data6 = "011100"); -- use a 6 bit end frame symbol
@@ -161,13 +169,15 @@ begin
                     when SYNCING      =>
                         if (sync_valid) then
                             state <= FRAME_BEGIN;
+                            busy <= True;
                         elsif (idle_valid) then
                             state <= IDLE;
                         end if;
 
                     when IDLE      =>
                         if (sync_valid) then
                             state <= FRAME_BEGIN;
+                            busy <= True;
                         elsif (idle_valid) then
                             state <= IDLE;
                         else
@@ -187,10 +197,13 @@ begin
                     when FRAME_END    =>
                         if (sync_valid) then
                             state <= FRAME_BEGIN;
+                            busy <= True;
                         elsif (idle_valid) then
                             state <= IDLE;
+                            busy <= False;
                         else
                             state <= SYNCING;
+                            busy <= False;
                         end if;
 
                     when others => state <= SYNCING;
@@ -253,6 +266,11 @@ begin
 
     data6 <= (others => '0'); -- not used in 16 bit mode
 
+    l1a         <= data_i (15);
+    reset_vfats <= data_i (14);
+    resync      <= data_i (13);
+    bc0         <= data_i (12);
+
     sync_valid <= data_i(11 downto 0) = x"ABC"; -- 12 bit DAV
     idle_valid <= data_i(11 downto 0) = x"AFA"; -- 12 bit idle
 
@@ -268,13 +286,15 @@ begin
                     when SYNCING      =>
                         if (sync_valid) then
                             state <= FRAME_BEGIN;
+                            busy <= True;
                         elsif (idle_valid) then
                             state <= IDLE;
                         end if;
 
                     when IDLE      =>
                         if (sync_valid) then
                             state <= FRAME_BEGIN;
+                            busy <= True;
                         elsif (idle_valid) then
                             state <= FRAME_BEGIN;
                         end if;
@@ -287,11 +307,14 @@ begin
 
                     when FRAME_END    =>
                         if (sync_valid) then
+                            busy <= True;
                             state <= FRAME_BEGIN;
                         elsif (idle_valid) then
                             state <= IDLE;
+                            busy <= False;
                         else
                             state <= SYNCING;
+                            busy <= False;
                         end if;
                     when others => state <= SYNCING;
                 end case;

src/gbt/gbt_serdes.vhd

@@ -61,7 +61,6 @@ architecture Behavioral of gbt_serdes is
     signal from_gbt          : std_logic_vector(15 downto 0) := (others => '0');
 
     signal to_gbt            : std_logic_vector(15 downto 0) := (others => '0');
-    signal to_gbt_polswap    : std_logic_vector(15 downto 0) := (others => '0');
     signal to_gbt_bitslipped : std_logic_vector(15 downto 0) := (others => '0');
     signal to_gbt_remap      : std_logic_vector(15 downto 0) := (others => '0');
     signal to_gbt_reg        : std_logic_vector(15 downto 0) := (others => '0');
@@ -153,25 +152,54 @@ begin
     --================--
 
     -- Input deserializer
-    i_from_gbt_des : entity work.from_gbt_des
+    i_from_gbt_des80 : entity work.from_gbt_des
     port map(
-        data_in_from_pins_p => elink_i_p,
-        data_in_from_pins_n => elink_i_n,
-        data_in_to_device   => from_gbt_raw,
+        data_in_from_pins_p => (elink_i_p(0 downto 0)),
+        data_in_from_pins_n => (elink_i_n(0 downto 0)),
+        data_in_to_device   => from_gbt_raw(7 downto 0),
         bitslip             => '0',
         clk_in              => iserdes_clk,
         clk_div_in          => iserdes_clkdiv,
         io_reset            => iserdes_reset
     );
 
+    -- Input deserializer
+    i_from_gbt_des320 : entity work.from_gbt_des
+    port map(
+        data_in_from_pins_p => elink_i_p(1 downto 1),
+        data_in_from_pins_n => elink_i_n(1 downto 1),
+        data_in_to_device   => from_gbt_raw(15 downto 8),
+        bitslip             => '0',
+        clk_in              => iserdes_clk,
+        clk_div_in          => iserdes_clkdiv,
+        io_reset            => iserdes_reset
+    );
+
+
 
     -- remap to account for how the Xilinx IPcore assigns the output pins
     -- flip-flop for routing and alignment
     process (iserdes_clkdiv) begin
         if (rising_edge(iserdes_clkdiv)) then
 
-            from_gbt_remapped <= from_gbt_raw(1) & from_gbt_raw(3) & from_gbt_raw(5) & from_gbt_raw(7) & from_gbt_raw(9) & from_gbt_raw(11) & from_gbt_raw(13) & from_gbt_raw(15)  &
-                                 from_gbt_raw(0) & from_gbt_raw(2) & from_gbt_raw(4) & from_gbt_raw(6) & from_gbt_raw(8) & from_gbt_raw(10) & from_gbt_raw(12) & from_gbt_raw(14);
+            -- 10 bit mapping
+            from_gbt_remapped <=
+                from_gbt_raw(12) &
+                from_gbt_raw(13) &
+                from_gbt_raw(14) &
+                from_gbt_raw(15) &
+                from_gbt_raw(8) &
+                from_gbt_raw(9) &
+                from_gbt_raw(10) &
+                from_gbt_raw(11) &
+                from_gbt_raw(0) &
+                from_gbt_raw(1) &
+                from_gbt_raw(2) &
+                from_gbt_raw(3) &
+                from_gbt_raw(4) &
+                from_gbt_raw(5) &
+                from_gbt_raw(6) &
+                from_gbt_raw(7);
 
             from_gbt <= from_gbt_remapped;
 
@@ -182,30 +210,14 @@ begin
     --== OUTPUT DATA ==--
     --=================--
 
-    -- tx polarity swaps
-
-    process(oserdes_clkdiv)
-    begin
-    if (rising_edge(oserdes_clkdiv)) then
-        if (reset='1') then
-            to_gbt_polswap <= (others => '0');
-        else
-
-            -- OH v3a has POLARITY SWAP on elink 1
-            to_gbt_polswap <= not to_gbt (15 downto 8) & to_gbt (7 downto 0);
-
-        end if;
-    end if;
-    end process;
-
     -- Bitslip the output to serializer
 
     i_gbt_tx_bitslip : entity work.gbt_tx_bitslip
     port map(
         fabric_clk  => oserdes_clkdiv,
         reset       => reset,
         bitslip_cnt => 0,
-        din         => to_gbt_polswap, -- 16 bit data input, synchronized to frame-clock
+        din         => to_gbt, -- 16 bit data input, synchronized to frame-clock
         dout        => to_gbt_bitslipped
     );
 
@@ -222,14 +234,8 @@ begin
             to_gbt_remap   <= (others => '0');
         else
 
-            to_gbt_remap <= to_gbt_bitslipped(8)  & to_gbt_bitslipped(0) &
-                            to_gbt_bitslipped(9)  & to_gbt_bitslipped(1) &
-                            to_gbt_bitslipped(10) & to_gbt_bitslipped(2) &
-                            to_gbt_bitslipped(11) & to_gbt_bitslipped(3) &
-                            to_gbt_bitslipped(12) & to_gbt_bitslipped(4) &
-                            to_gbt_bitslipped(13) & to_gbt_bitslipped(5) &
-                            to_gbt_bitslipped(14) & to_gbt_bitslipped(6) &
-                            to_gbt_bitslipped(15) & to_gbt_bitslipped(7);
+            to_gbt_remap <=  to_gbt_bitslipped;
+
         end if;
     end if;
     end process;
@@ -253,11 +259,22 @@ begin
     -- Output serializer
     -- we want to output the data on the falling edge of the clock so that the GBT can sample on the rising edge
 
-    i_to_gbt_ser : entity work.to_gbt_ser
+    i_to_gbt_ser80 : entity work.to_gbt_ser
+    port map(
+        data_out_from_device    => to_gbt_reg(7 downto 0),
+        data_out_to_pins_p      => elink_o_p(0 downto 0),
+        data_out_to_pins_n      => elink_o_n(0 downto 0),
+        clk_in                  => oserdes_clk,
+        clk_div_in              => oserdes_clkdiv,
+        io_reset                => oserdes_reset
+    );
+
+    i_to_gbt_ser320 : entity work.to_gbt_ser
     port map(
-        data_out_from_device    => to_gbt_reg,
-        data_out_to_pins_p      => elink_o_p,
-        data_out_to_pins_n      => elink_o_n,
+        -- POLARITY SWAP ON ELINK #1
+        data_out_from_device    => (not (to_gbt_reg (15 downto 8))),
+        data_out_to_pins_p      => elink_o_p(1 downto 1),
+        data_out_to_pins_n      => elink_o_n(1 downto 1),
         clk_in                  => oserdes_clk,
         clk_div_in              => oserdes_clkdiv,
         io_reset                => oserdes_reset

src/ip_cores/clk_gen.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:29:18 2017
+# Date: Sat Nov 11 20:38:35 2017
 #
 ##############################################################
 #

src/ip_cores/eprt_clk_gen.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:30:17 2017
+# Date: Sat Nov 11 20:39:40 2017
 #
 ##############################################################
 #

src/ip_cores/fifo_request_rx.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:31:29 2017
+# Date: Sat Nov 11 20:41:20 2017
 #
 ##############################################################
 #

src/ip_cores/fifo_request_tx.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:33:05 2017
+# Date: Sat Nov 11 20:43:41 2017
 #
 ##############################################################
 #

src/ip_cores/from_gbt_des.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:29:55 2017
+# Date: Sat Nov 11 20:39:15 2017
 #
 ##############################################################
 #
@@ -63,7 +63,7 @@ CSET iddr_rst_type=ASYNC
 CSET interface_type=NETWORKING
 CSET notes=None
 CSET serialization_factor=8
-CSET system_data_width=2
+CSET system_data_width=1
 CSET train_constant=0
 CSET use_phase_detector=false
 CSET use_serialization=true
@@ -85,4 +85,4 @@ CSET v6_oddr_alignment=SAME_EDGE
 MISC pkg_timestamp=2012-03-26T12:54:40Z
 # END Extra information
 GENERATE
-# CRC: 1b542252
+# CRC: 26f0fbf4

src/ip_cores/gbt_cdc_fifo.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:34:52 2017
+# Date: Sat Nov 11 20:46:12 2017
 #
 ##############################################################
 #

src/ip_cores/sem.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:30:41 2017
+# Date: Sat Nov 11 20:40:13 2017
 #
 ##############################################################
 #

src/ip_cores/to_gbt_ser.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:29:43 2017
+# Date: Sat Nov 11 20:39:02 2017
 #
 ##############################################################
 #
@@ -63,7 +63,7 @@ CSET iddr_rst_type=ASYNC
 CSET interface_type=NETWORKING
 CSET notes=None
 CSET serialization_factor=8
-CSET system_data_width=2
+CSET system_data_width=1
 CSET train_constant=0
 CSET use_phase_detector=false
 CSET use_serialization=true
@@ -85,4 +85,4 @@ CSET v6_oddr_alignment=SAME_EDGE
 MISC pkg_timestamp=2012-03-26T12:54:40Z
 # END Extra information
 GENERATE
-# CRC: 15b30168
+# CRC: 49073920

src/ip_cores/xadc.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Sat Nov 04 00:34:35 2017
+# Date: Sat Nov 11 20:45:50 2017
 #
 ##############################################################
 #