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Merge pull request #22 from andrewpeck/devel
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v3.2.6
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@andrewpeck
andrewpeck authored Jul 31, 2019
2 parents 076ef15 + 21e75fd commit de70e54
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7 changes: 5 additions & 2 deletions .gitignore
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.Xil

*.xcix
src/ip_cores_a7/*
src/ip_cores/*
src/ip_cores_a7/*/*
!src/ip_cores_a7/*/*.xci

src/ip_cores/*
!src/ip_cores/*.xco

!src/ip_cores/*/*.xco

tags

iseconfig
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12 changes: 6 additions & 6 deletions ...Hv3c_GBT_0__2019-05-08_FINAL_no_delay.txt → ...c_GBT_0__2019-06-19_FINAL_80MHzRefClk.txt
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96 changes: 66 additions & 30 deletions doc/latex/address_table.tex
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Expand Up @@ -23,7 +23,7 @@

\title{Optohybrid v3 Address Table}
% START: ADDRESS_TABLE_VERSION :: DO NOT EDIT
\author{\textbf{GE1/1 Long} \\ \\ v03.02.03.1C \\ 20190508}
\author{\textbf{GE1/1 Short} \\ \\ v03.02.06.0C \\ 20190728}
% END: ADDRESS_TABLE_VERSION :: DO NOT EDIT
\begin{document}

Expand Down Expand Up @@ -462,30 +462,30 @@
\hline
\textbf{Node} & \textbf{Adr} & \textbf{Bits} & \textbf{Dir} & \textbf{Def} & \textbf{Description} \\\hline
\nopagebreak
VFAT0 & \texttt{0x2017} & \texttt{[31:0]} & r & \texttt{} & VFAT 0 Counter \\\hline
VFAT1 & \texttt{0x2018} & \texttt{[31:0]} & r & \texttt{} & VFAT 1 Counter \\\hline
VFAT2 & \texttt{0x2019} & \texttt{[31:0]} & r & \texttt{} & VFAT 2 Counter \\\hline
VFAT3 & \texttt{0x201a} & \texttt{[31:0]} & r & \texttt{} & VFAT 3 Counter \\\hline
VFAT4 & \texttt{0x201b} & \texttt{[31:0]} & r & \texttt{} & VFAT 4 Counter \\\hline
VFAT5 & \texttt{0x201c} & \texttt{[31:0]} & r & \texttt{} & VFAT 5 Counter \\\hline
VFAT6 & \texttt{0x201d} & \texttt{[31:0]} & r & \texttt{} & VFAT 6 Counter \\\hline
VFAT7 & \texttt{0x201e} & \texttt{[31:0]} & r & \texttt{} & VFAT 7 Counter \\\hline
VFAT8 & \texttt{0x201f} & \texttt{[31:0]} & r & \texttt{} & VFAT 8 Counter \\\hline
VFAT9 & \texttt{0x2020} & \texttt{[31:0]} & r & \texttt{} & VFAT 9 Counter \\\hline
VFAT10 & \texttt{0x2021} & \texttt{[31:0]} & r & \texttt{} & VFAT 10 Counter \\\hline
VFAT11 & \texttt{0x2022} & \texttt{[31:0]} & r & \texttt{} & VFAT 11 Counter \\\hline
VFAT12 & \texttt{0x2023} & \texttt{[31:0]} & r & \texttt{} & VFAT 12 Counter \\\hline
VFAT13 & \texttt{0x2024} & \texttt{[31:0]} & r & \texttt{} & VFAT 13 Counter \\\hline
VFAT14 & \texttt{0x2025} & \texttt{[31:0]} & r & \texttt{} & VFAT 14 Counter \\\hline
VFAT15 & \texttt{0x2026} & \texttt{[31:0]} & r & \texttt{} & VFAT 15 Counter \\\hline
VFAT16 & \texttt{0x2027} & \texttt{[31:0]} & r & \texttt{} & VFAT 16 Counter \\\hline
VFAT17 & \texttt{0x2028} & \texttt{[31:0]} & r & \texttt{} & VFAT 17 Counter \\\hline
VFAT18 & \texttt{0x2029} & \texttt{[31:0]} & r & \texttt{} & VFAT 18 Counter \\\hline
VFAT19 & \texttt{0x202a} & \texttt{[31:0]} & r & \texttt{} & VFAT 19 Counter \\\hline
VFAT20 & \texttt{0x202b} & \texttt{[31:0]} & r & \texttt{} & VFAT 20 Counter \\\hline
VFAT21 & \texttt{0x202c} & \texttt{[31:0]} & r & \texttt{} & VFAT 21 Counter \\\hline
VFAT22 & \texttt{0x202d} & \texttt{[31:0]} & r & \texttt{} & VFAT 22 Counter \\\hline
VFAT23 & \texttt{0x202e} & \texttt{[31:0]} & r & \texttt{} & VFAT 23 Counter \\\hline
VFAT0\_SBITS & \texttt{0x2017} & \texttt{[31:0]} & r & \texttt{} & VFAT 0 Counter \\\hline
VFAT1\_SBITS & \texttt{0x2018} & \texttt{[31:0]} & r & \texttt{} & VFAT 1 Counter \\\hline
VFAT2\_SBITS & \texttt{0x2019} & \texttt{[31:0]} & r & \texttt{} & VFAT 2 Counter \\\hline
VFAT3\_SBITS & \texttt{0x201a} & \texttt{[31:0]} & r & \texttt{} & VFAT 3 Counter \\\hline
VFAT4\_SBITS & \texttt{0x201b} & \texttt{[31:0]} & r & \texttt{} & VFAT 4 Counter \\\hline
VFAT5\_SBITS & \texttt{0x201c} & \texttt{[31:0]} & r & \texttt{} & VFAT 5 Counter \\\hline
VFAT6\_SBITS & \texttt{0x201d} & \texttt{[31:0]} & r & \texttt{} & VFAT 6 Counter \\\hline
VFAT7\_SBITS & \texttt{0x201e} & \texttt{[31:0]} & r & \texttt{} & VFAT 7 Counter \\\hline
VFAT8\_SBITS & \texttt{0x201f} & \texttt{[31:0]} & r & \texttt{} & VFAT 8 Counter \\\hline
VFAT9\_SBITS & \texttt{0x2020} & \texttt{[31:0]} & r & \texttt{} & VFAT 9 Counter \\\hline
VFAT10\_SBITS & \texttt{0x2021} & \texttt{[31:0]} & r & \texttt{} & VFAT 10 Counter \\\hline
VFAT11\_SBITS & \texttt{0x2022} & \texttt{[31:0]} & r & \texttt{} & VFAT 11 Counter \\\hline
VFAT12\_SBITS & \texttt{0x2023} & \texttt{[31:0]} & r & \texttt{} & VFAT 12 Counter \\\hline
VFAT13\_SBITS & \texttt{0x2024} & \texttt{[31:0]} & r & \texttt{} & VFAT 13 Counter \\\hline
VFAT14\_SBITS & \texttt{0x2025} & \texttt{[31:0]} & r & \texttt{} & VFAT 14 Counter \\\hline
VFAT15\_SBITS & \texttt{0x2026} & \texttt{[31:0]} & r & \texttt{} & VFAT 15 Counter \\\hline
VFAT16\_SBITS & \texttt{0x2027} & \texttt{[31:0]} & r & \texttt{} & VFAT 16 Counter \\\hline
VFAT17\_SBITS & \texttt{0x2028} & \texttt{[31:0]} & r & \texttt{} & VFAT 17 Counter \\\hline
VFAT18\_SBITS & \texttt{0x2029} & \texttt{[31:0]} & r & \texttt{} & VFAT 18 Counter \\\hline
VFAT19\_SBITS & \texttt{0x202a} & \texttt{[31:0]} & r & \texttt{} & VFAT 19 Counter \\\hline
VFAT20\_SBITS & \texttt{0x202b} & \texttt{[31:0]} & r & \texttt{} & VFAT 20 Counter \\\hline
VFAT21\_SBITS & \texttt{0x202c} & \texttt{[31:0]} & r & \texttt{} & VFAT 21 Counter \\\hline
VFAT22\_SBITS & \texttt{0x202d} & \texttt{[31:0]} & r & \texttt{} & VFAT 22 Counter \\\hline
VFAT23\_SBITS & \texttt{0x202e} & \texttt{[31:0]} & r & \texttt{} & VFAT 23 Counter \\\hline
RESET & \texttt{0x202f} & \texttt{[0:0]} & w & Pulsed & Reset S-bit counters \\\hline
SBIT\_CNT\_PERSIST & \texttt{0x2030} & \texttt{[0:0]} & rw & \texttt{0x0} & 1=counters will persist until manually reset; \\ & & & & & 0=counters will automatically reset at CNT\_TIME \\\hline
SBIT\_CNT\_TIME\_MAX & \texttt{0x2031} & \texttt{[31:0]} & rw & \texttt{0x2638E98} & Number of BX that the VFAT S-bit counters will count to before automatically resetting to zero \\\hline
Expand Down Expand Up @@ -808,6 +808,45 @@
\vspace{5mm}


\noindent
\subsection*{\textcolor{parentcolor}{\textbf{FPGA.TRIG.SBIT\_HITMAP}}}

\vspace{4mm}
\noindent
The Sbit hitmap module accumulates all incoming Sbits during a period of time
\noindent

\keepXColumns
\begin{tabularx}{\linewidth}{ | l | l | r | c | l | X | }
\hline
\textbf{Node} & \textbf{Adr} & \textbf{Bits} & \textbf{Dir} & \textbf{Def} & \textbf{Description} \\\hline
\nopagebreak
RESET & \texttt{0x20b0} & \texttt{[31:0]} & w & Pulsed & Reset the accumulation registers \\\hline
ACQUIRE & \texttt{0x20b1} & \texttt{[0:0]} & rw & \texttt{0x0} & Sbits are accumulated as long as this flag is set \\\hline
VFAT0\_MSB & \texttt{0x20b2} & \texttt{[31:0]} & r & \texttt{} & Accumulator for Sbit 63 to 32 of VFAT\{VFAT\_IDX\} \\\hline
VFAT0\_LSB & \texttt{0x20b3} & \texttt{[31:0]} & r & \texttt{} & Accumulator for Sbit 31 to 0 of VFAT\{VFAT\_IDX\} \\\hline
\end{tabularx}
\vspace{5mm}


\noindent
\subsection*{\textcolor{parentcolor}{\textbf{FPGA.TRIG.CTRL}}}

\vspace{4mm}
\noindent
Controls and monitors various parameters of the S-bit deserialization and cluster building.
\noindent

\keepXColumns
\begin{tabularx}{\linewidth}{ | l | l | r | c | l | X | }
\hline
\textbf{Node} & \textbf{Adr} & \textbf{Bits} & \textbf{Dir} & \textbf{Def} & \textbf{Description} \\\hline
\nopagebreak
SBIT\_SOT\_INVALID\_BITSKIP & \texttt{0x20e2} & \texttt{[23:0]} & r & \texttt{} & 24 bit list of VFATs with a invalid bitskip counter for Start-of-frame pulses \\\hline
\end{tabularx}
\vspace{5mm}



\pagebreak
\section{Module: FPGA.CLOCKING \hfill \texttt{0x3000}}
Expand All @@ -828,10 +867,8 @@
\hline
\textbf{Node} & \textbf{Adr} & \textbf{Bits} & \textbf{Dir} & \textbf{Def} & \textbf{Description} \\\hline
\nopagebreak
GBT\_MMCM\_LOCKED & \texttt{0x3000} & \texttt{[0:0]} & r & \texttt{} & GBT deserialization MMCM locked \\\hline
LOGIC\_MMCM\_LOCKED & \texttt{0x3000} & \texttt{[1:1]} & r & \texttt{} & User logic MMCM locked \\\hline
GBT\_MMCM\_UNLOCKED\_CNT & \texttt{0x3000} & \texttt{[23:16]} & r & \texttt{} & GBT deserialization MMCM unlocked cnt \\\hline
LOGIC\_MMCM\_UNLOCKED\_CNT & \texttt{0x3000} & \texttt{[31:24]} & r & \texttt{} & User logic MMCM unlocked cnt \\\hline
MMCM\_LOCKED & \texttt{0x3000} & \texttt{[0:0]} & r & \texttt{} & MMCM locked \\\hline
MMCM\_UNLOCKED\_CNT & \texttt{0x3000} & \texttt{[23:16]} & r & \texttt{} & MMCM unlocked cnt \\\hline
\end{tabularx}
\vspace{5mm}

Expand All @@ -858,7 +895,6 @@
\nopagebreak
CNT\_RESPONSE\_SENT & \texttt{0x4000} & \texttt{[31:8]} & r & \texttt{} & Number of wishbone responses sent back \\\hline
TX\_READY & \texttt{0x4001} & \texttt{[0:0]} & r & \texttt{} & GBT TX READY from GBTx Chip \\\hline
TX\_DELAY & \texttt{0x4001} & \texttt{[8:4]} & rw & \texttt{0x0} & GBT TX IODELAY in 78 ps steps, 0-31 \\\hline
\end{tabularx}
\vspace{5mm}

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97 changes: 53 additions & 44 deletions optohybrid_registers.xml
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Expand Up @@ -382,7 +382,7 @@
fw_reg_addr_msb="7"
fw_reg_addr_lsb="0">

<node id="CTRL" address="0x0" description = "Controls and monitors various parameters of the S-bit deserialization and cluster building.">
<node id="CTRL" address="0x0" description = "Controls and monitors various parameters of the S-bit deserialization and cluster building.">

<!-- updated by update_vfat_counters.py-->
<!-- START: VFAT_MASK DO NOT EDIT -->
Expand All @@ -393,11 +393,11 @@
fw_default="0x0"/>
<!-- END: VFAT_MASK DO NOT EDIT -->

<node id="SBIT_DEADTIME" address="0x0" permission="rw"
description="Set programmable oneshot deadtime which applies to retriggers on individual VFAT channels"
fw_signal="trig_deadtime"
mask="0x0f000000"
fw_default="0x7"/>
<node id="SBIT_DEADTIME" address="0x0" permission="rw"
description="Set programmable oneshot deadtime which applies to retriggers on individual VFAT channels"
fw_signal="trig_deadtime"
mask="0x0f000000"
fw_default="0x7"/>

<!-- updated by update_vfat_counters.py-->
<!-- START: ACTIVE_VFATS DO NOT EDIT -->
Expand All @@ -407,16 +407,22 @@
fw_signal="active_vfats"/>
<!-- END: ACTIVE_VFATS DO NOT EDIT -->

<node id="CNT_OVERFLOW" address="0x2" permission="r"
mask="0xffff"
description="Overflow Counter (more than 8 clusters in a bx)"
fw_cnt_en_signal="sbit_overflow"
fw_cnt_reset_signal="cnt_reset"
fw_cnt_snap_signal="cnt_snap"
fw_signal="cnt_sbit_overflow"/>
<node id="CNT_OVERFLOW" address="0x2" permission="r"
mask="0xffff"
description="Overflow Counter (more than 8 clusters in a bx)"
fw_cnt_en_signal="sbit_overflow"
fw_cnt_reset_signal="cnt_reset"
fw_cnt_snap_signal="cnt_snap"
fw_signal="cnt_sbit_overflow"/>

<node id="ALIGNED_COUNT_TO_READY" address="0x2" permission="rw"
description="Number of link consecutive good frames required before the transmission unit is marked as good and S-bits can be produced"
fw_signal="aligned_count_to_ready"
mask="0xfff0000"
fw_default="0x1ff"/>

<!-- updated by update_vfat_counters.py-->
<!-- START: SOT_READY_UNSTABLE DO NOT EDIT -->
<!-- START: SOT_STATUS DO NOT EDIT -->
<node id="SBIT_SOT_READY" address="0x3" permission="r"
description="24 bit list of VFATs with stable Start-of-frame pulses (in sync for a number of clock cycles)"
mask="0xffffff"
Expand All @@ -425,16 +431,14 @@
description="24 bit list of VFATs with unstable Start-of-frame pulses (became misaligned after already achieving lock)"
mask="0xffffff"
fw_signal="sot_unstable" />
<!-- END: SOT_READY_UNSTABLE DO NOT EDIT -->

<node id="SBIT_SOT_INVALID_BITSKIP" address="0xe2" permission="r"
description="24 bit list of VFATs with a invalid bitskip counter for Start-of-frame pulses"
mask="0xffffff"
fw_signal="sot_invalid_bitskip" />
<!-- END: SOT_STATUS DO NOT EDIT -->

<node id="ALIGNED_COUNT_TO_READY" address="0x2" permission="rw"
description="Number of link consecutive good frames required before the transmission unit is marked as good and S-bits can be produced"
fw_signal="aligned_count_to_ready"
mask="0xfff0000"
fw_default="0x1ff"/>

<node id="INVERT" address="0x5" description="Controls the polarity of S-bit signals to account for polarity swaps on the GEB or OH">
<node id="INVERT" address="0x5" description="Controls the polarity of S-bit signals to account for polarity swaps on the GEB or OH">
<!-- START: INVERT_REGS DO NOT EDIT -->
<node id="SOT_INVERT" address="0x0" permission="rw"
description="1=invert pair"
Expand Down Expand Up @@ -715,7 +719,7 @@

<!-- updated by update_vfat_counters.py-->
<!-- START: VFAT_COUNTERS DO NOT EDIT -->
<node id="VFAT${VFAT_CNT_IDX}" address="0x0" permission="r"
<node id="VFAT${VFAT_CNT_IDX}_SBITS" address="0x0" permission="r"
mask="0xffffffff"
description="VFAT ${VFAT_CNT_IDX} Counter"
fw_cnt_en_signal="active_vfats(${VFAT_CNT_IDX})"
Expand Down Expand Up @@ -1943,6 +1947,25 @@
fw_signal="sbitmon_l1a_delay"/>
</node>

<node id="SBIT_HITMAP" address="0xb0"
description="The Sbit hitmap module accumulates all incoming Sbits during a period of time">
<node id="RESET" address="0x0" permission="w"
description="Reset the accumulation registers"
fw_write_pulse_signal="hitmap_reset"/>
<node id="ACQUIRE" address="0x1" mask="0x1" permission="rw"
description="Sbits are accumulated as long as this flag is set"
fw_signal="hitmap_acquire"
fw_default="0x0"/>
<node id="VFAT${VFAT_IDX}_MSB" address="0x2" mask="0xffffffff" permission="r"
description="Accumulator for Sbit 63 to 32 of VFAT{VFAT_IDX}"
fw_signal="hitmap_sbits(${VFAT_IDX})(63 downto 32)"
generate="true" generate_size="24" generate_address_step="0x2" generate_idx_var="VFAT_IDX"/>
<node id="VFAT${VFAT_IDX}_LSB" address="0x3" mask="0xffffffff" permission="r"
description="Accumulator for Sbit 31 to 0 of VFAT{VFAT_IDX}"
fw_signal="hitmap_sbits(${VFAT_IDX})(31 downto 0)"
generate="true" generate_size="24" generate_address_step="0x2" generate_idx_var="VFAT_IDX"/>
</node>

</node> <!--TRIG-->

<!--Clocking module -->
Expand All @@ -1958,24 +1981,15 @@
fw_reg_addr_msb="1"
fw_reg_addr_lsb="0">

<node id="GBT_MMCM_LOCKED" address="0x0" permission="r"
<node id="MMCM_LOCKED" address="0x0" permission="r"
mask="0x00000001"
description="GBT deserialization MMCM locked"
fw_signal="mmcm_locked(1)"/>
<node id="LOGIC_MMCM_LOCKED" address="0x0" permission="r"
mask="0x00000002"
description="User logic MMCM locked"
fw_signal="mmcm_locked(0)"/>
<node id="GBT_MMCM_UNLOCKED_CNT" address="0x0" permission="r"
description="MMCM locked"
fw_signal="mmcm_locked"/>
<node id="MMCM_UNLOCKED_CNT" address="0x0" permission="r"
mask="0x00ff0000"
description="GBT deserialization MMCM unlocked cnt"
fw_cnt_en_signal="mmcm_unlocked(1)"
fw_signal="cnt_eprt_mmcm_unlocked"/>
<node id="LOGIC_MMCM_UNLOCKED_CNT" address="0x0" permission="r"
mask="0xff000000"
description="User logic MMCM unlocked cnt"
fw_cnt_en_signal="mmcm_unlocked(0)"
fw_signal="cnt_dskw_mmcm_unlocked"/>
description="MMCM unlocked cnt"
fw_cnt_en_signal="not mmcm_locked"
fw_signal="mmcm_unlocked"/>
</node>

<!--GBT module -->
Expand Down Expand Up @@ -2003,11 +2017,6 @@
mask="0x00000001"
description="GBT TX READY from GBTx Chip"
fw_signal="gbt_txready_i"/>
<node id="TX_DELAY" address="0x1" permission="rw"
mask="0x1f0"
description="GBT TX IODELAY in 78 ps steps, 0-31"
fw_default="0x0"
fw_signal="tx_delay"/>
</node> <!--TX-->

<node id="RX" address="0x4" description = "Controls and monitors the transmit link from the GBTx to the FPGA">
Expand Down
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