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compulab: dts: imx8plus: correct pad settings
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According to SOC's TRM bit layout, BIT3 and BIT0 are reserved:
 8  7   6   5   4   3  2 1  0
PE HYS PUE ODE FSEL X  DSE  X

This patch corrects pad settings for C-Lab products based on imx8plus SOC.
Sync with compulab-linux.

Signed-off-by: Ilya Ledvich <[email protected]>
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@ilyacompulab
ilyacompulab committed Mar 18, 2024
1 parent 7acba54 commit d0cb0f6
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Showing 6 changed files with 223 additions and 223 deletions.
118 changes: 59 additions & 59 deletions arch/arm/dts/mcm-imx8m-plus.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -439,44 +439,44 @@

pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
>;
};

pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
/* gpio */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* WOL */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x19 /* INT */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x19 /* RST */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* WOL */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x10 /* INT */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x10 /* RST */
>;
};

Expand All @@ -493,69 +493,69 @@

pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
>;
};

pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};

pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};

pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};

pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c3
MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c2
MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2
>;
};

pinctrl_i2c1_gpio: i2c1grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2
>;
};

pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2
>;
};

pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2
>;
};

pinctrl_i2c5_gpio: i2c5grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x1c3
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1c3
MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x1c2
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1c2
>;
};

pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
>;
};

Expand All @@ -573,27 +573,27 @@

pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x140
>;
};

pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49
MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x140
>;
};

pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};

pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
>;
};

Expand All @@ -605,7 +605,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};

Expand All @@ -617,7 +617,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};

Expand All @@ -629,7 +629,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};

Expand Down
4 changes: 2 additions & 2 deletions arch/arm/dts/sb-iotdimx8p.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -124,13 +124,13 @@
&iomuxc {
pinctrl_fec_phy_reset: fecphyrstgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x19
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10
>;
};

pinctrl_usb_hub_rst: usbhubrstgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x100
>;
};

Expand Down
6 changes: 3 additions & 3 deletions arch/arm/dts/sb-iotgimx8plus.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -125,13 +125,13 @@
&iomuxc {
pinctrl_fec_phy_reset: fecphyrstgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x19
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10
>;
};

pinctrl_usb_hub_rst: usbhubrstgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x100
>;
};

Expand All @@ -149,7 +149,7 @@

pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x101
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x100
>;
};
};
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