[Intel][ARL] Declare PCI ids to probe the IMC as a MTL controller

cyring · Oct 13, 2024 · bd528a9 · bd528a9
1 parent 2f2e041
commit bd528a9
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Showing 4 changed files with 41 additions and 3 deletions.
diff --git a/x86_64/corefreq-api.h b/x86_64/corefreq-api.h
@@ -1556,6 +1556,11 @@ typedef struct
 #define DID_INTEL_METEORLAKE_UT4_PCH	0x7e07
 /* Source: Arrow Lake Client Platform/MTL-S (0x6-0xc6, stepping: 0x0)	*/
 #define DID_INTEL_ARL_MTL_PCH_S_SMBUS	0x7f23
+/* Source: Intel Core Ultra 200S | ASRock Z890 Taichi OCF		*/
+#define DID_INTEL_ARROWLAKE_S_8_16_HB	0x7d1a
+#define DID_INTEL_ARROWLAKE_S_8_12_HB	0x7d1b
+#define DID_INTEL_ARROWLAKE_S_6_8_HB	0x7d2a
+#define DID_INTEL_ARROWLAKE_S_PCH	0xae0d
 /* Source: /include/linux/pci_ids.h					*/
 #define DID_AMD_K8_NB_MEMCTL		0x1102
 #define DID_AMD_K8_NB			0x1100

diff --git a/x86_64/corefreq.h b/x86_64/corefreq.h
@@ -89,6 +89,7 @@ enum CHIPSET {
 	IC_MTL_H,
 	IC_MTL_U,
 	IC_MTL_UT4,
+	IC_ARL_S,
 	IC_K8,
 	IC_ZEN,
 	CHIPSETS

diff --git a/x86_64/corefreqd.c b/x86_64/corefreqd.c
@@ -6376,6 +6376,9 @@ void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
   }
 }
 
+#define ARL_CAP MTL_CAP
+#define ARL_IMC MTL_IMC
+
 void AMD_0Fh_MCH(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 {
     struct {
@@ -7055,6 +7058,7 @@ static char *Chipset[CHIPSETS] = {
 	[IC_MTL_H]		= "Intel MTL-H",
 	[IC_MTL_U]		= "Intel MTL-U",
 	[IC_MTL_UT4]		= "Intel MTL-U Type4",
+	[IC_ARL_S]		= "Intel ARL-S",
 	[IC_K8] 		= "K8/HyperTransport",
 	[IC_ZEN]		= "Zen UMC"
 };
@@ -7625,6 +7629,15 @@ void PCI_Intel(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core),
 	case DID_INTEL_METEORLAKE_UT4_PCH:
 		SET_CHIPSET(IC_MTL_UT4);
 		break;
+	case DID_INTEL_ARROWLAKE_S_8_16_HB:
+	case DID_INTEL_ARROWLAKE_S_8_12_HB:
+	case DID_INTEL_ARROWLAKE_S_6_8_HB:
+		ARL_CAP(RO(Shm), RO(Proc), RO(Core));
+		ARL_IMC(RO(Shm), RO(Proc));
+		break;
+	case DID_INTEL_ARROWLAKE_S_PCH:
+		SET_CHIPSET(IC_ARL_S);
+		break;
 	}
 }
 

diff --git a/x86_64/corefreqk.h b/x86_64/corefreqk.h
@@ -2165,6 +2165,8 @@ static PCI_CALLBACK GLK_IMC(struct pci_dev *dev) ;
 #define RPL_PCH CML_PCH
 static PCI_CALLBACK MTL_IMC(struct pci_dev *dev) ;
 #define MTL_PCH CML_PCH
+#define ARL_IMC MTL_IMC
+#define ARL_PCH MTL_PCH
 static PCI_CALLBACK AMD_0Fh_MCH(struct pci_dev *dev) ;
 static PCI_CALLBACK AMD_0Fh_HTT(struct pci_dev *dev) ;
 static PCI_CALLBACK AMD_Zen_IOMMU(struct pci_dev *dev) ;
@@ -3162,6 +3164,23 @@ static struct pci_device_id PCI_MTL_ids[] = {
 		PCI_VDEVICE(INTEL, DID_INTEL_METEORLAKE_UT4_PCH),
 		.driver_data = (kernel_ulong_t) MTL_PCH
 	},
+/* Arrow Lake */
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_ARROWLAKE_S_8_16_HB),
+		.driver_data = (kernel_ulong_t) ARL_IMC
+	},
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_ARROWLAKE_S_8_12_HB),
+		.driver_data = (kernel_ulong_t) ARL_IMC
+	},
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_ARROWLAKE_S_6_8_HB),
+		.driver_data = (kernel_ulong_t) ARL_IMC
+	},
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_ARROWLAKE_S_PCH),
+		.driver_data = (kernel_ulong_t) ARL_PCH
+	},
 	{0, }
 };
 
@@ -12014,7 +12033,7 @@ static ARCH Arch[ARCHITECTURES] = {
 	.thermalFormula = THERMAL_FORMULA_INTEL,
 	.voltageFormula = VOLTAGE_FORMULA_INTEL_SAV,
 	.powerFormula   = POWER_FORMULA_INTEL,
-	.PCI_ids = PCI_Void_ids,
+	.PCI_ids = PCI_MTL_ids,
 	.Uncore = {
 		.Start = Start_Uncore_Alderlake,
 		.Stop = Stop_Uncore_Alderlake,
@@ -12038,7 +12057,7 @@ static ARCH Arch[ARCHITECTURES] = {
 	.thermalFormula = THERMAL_FORMULA_INTEL,
 	.voltageFormula = VOLTAGE_FORMULA_INTEL_SAV,
 	.powerFormula   = POWER_FORMULA_INTEL,
-	.PCI_ids = PCI_Void_ids,
+	.PCI_ids = PCI_MTL_ids,
 	.Uncore = {
 		.Start = Start_Uncore_Alderlake,
 		.Stop = Stop_Uncore_Alderlake,
@@ -12062,7 +12081,7 @@ static ARCH Arch[ARCHITECTURES] = {
 	.thermalFormula = THERMAL_FORMULA_INTEL,
 	.voltageFormula = VOLTAGE_FORMULA_INTEL_SAV,
 	.powerFormula   = POWER_FORMULA_INTEL,
-	.PCI_ids = PCI_Void_ids,
+	.PCI_ids = PCI_MTL_ids,
 	.Uncore = {
 		.Start = Start_Uncore_Alderlake,
 		.Stop = Stop_Uncore_Alderlake,