Draft: Add m-mode CLIC interrupt testcases

This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <[email protected]>
dansmathers · Feb 8, 2024 · 11afbf0 · 11afbf0
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diff --git a/riscv-test-suite/rv32i_m/Smclic/src/clicdirect-01.S b/riscv-test-suite/rv32i_m/Smclic/src/clicdirect-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-01.S b/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-02.S b/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-02.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-03.S b/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-03.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-04.S b/riscv-test-suite/rv32i_m/Smclic/src/cliclevel-04.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/clicnomint-01.S b/riscv-test-suite/rv32i_m/Smclic/src/clicnomint-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/clicnomint-02.S b/riscv-test-suite/rv32i_m/Smclic/src/clicnomint-02.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/clicnomint-03.S b/riscv-test-suite/rv32i_m/Smclic/src/clicnomint-03.S
diff --git a/riscv-test-suite/rv32i_m/Smclic/src/clicwfi-01.S b/riscv-test-suite/rv32i_m/Smclic/src/clicwfi-01.S