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Draft: Add m/s-mode CLIC interrupt testcases
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This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <[email protected]>
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dansmathers authored and jamesbeyond committed Jun 6, 2024
1 parent 35ee9c1 commit 2e3b80b
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54 changes: 54 additions & 0 deletions coverage/rvi_smclic.cgf
Original file line number Diff line number Diff line change
@@ -0,0 +1,54 @@
clicdirect-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

cliclevel-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

cliclevel-02:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

cliclevel-03:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

cliclevel-04:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

clicnomint-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

clicnomint-02:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

clicnomint-03:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

clicwfi-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

96 changes: 96 additions & 0 deletions coverage/rvi_ssclic.cgf
Original file line number Diff line number Diff line change
@@ -0,0 +1,96 @@
sclicdeleg-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicmdisable-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

sclicmdisable-02:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

sclicmdisable-03:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

sclicnodeleg-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicorder-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicorder-02:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicorder-03:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicorder-04:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicprivorder-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicprivorder-02:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicprivorder-03:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

sclicsdisable-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

sclicsdisable-02:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

sclicsdisable-03:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 0: 0

sclicwfi-01:
config:
- check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True
csr_comb:
mcause >> (xlen-1) == 1: 0

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