Add interrupt test cases using clint MSW and MTIMER interrupts

requires riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 To include these tests in riscof testlist flow, add Smclint to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclint Signed-off-by: Dan Smathers <[email protected]>
dansmathers · Feb 6, 2024 · 6642c22 · 6642c22
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diff --git a/riscv-test-suite/rv32i_m/Smclint/src/direct-01.S b/riscv-test-suite/rv32i_m/Smclint/src/direct-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/direct-02.S b/riscv-test-suite/rv32i_m/Smclint/src/direct-02.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/ecall-01.S b/riscv-test-suite/rv32i_m/Smclint/src/ecall-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-01.S b/riscv-test-suite/rv32i_m/Smclint/src/level-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-02.S b/riscv-test-suite/rv32i_m/Smclint/src/level-02.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-03.S b/riscv-test-suite/rv32i_m/Smclint/src/level-03.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-04.S b/riscv-test-suite/rv32i_m/Smclint/src/level-04.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/msw-01.S b/riscv-test-suite/rv32i_m/Smclint/src/msw-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/mtimer-01.S b/riscv-test-suite/rv32i_m/Smclint/src/mtimer-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/nomint-01.S b/riscv-test-suite/rv32i_m/Smclint/src/nomint-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/nomint-02.S b/riscv-test-suite/rv32i_m/Smclint/src/nomint-02.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/vectored-01.S b/riscv-test-suite/rv32i_m/Smclint/src/vectored-01.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/vectored-02.S b/riscv-test-suite/rv32i_m/Smclint/src/vectored-02.S
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/wfi-01.S b/riscv-test-suite/rv32i_m/Smclint/src/wfi-01.S