[JIT] Add legacy extended EVEX encoding and EVEX.ND feature to x64 emitter backend #108796
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1. Emitter unit testsJIT disassembler outputs: LLVM disassembler outputs: No disassemble diff observed: |
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2. SuperPMIVerification with SuperPMI: asmdiffs: MISSED contexts: base: 0 (0.00%), diff: 11 (0.00%) Diff JIT options: JitBypassAPXCheck=1 Overall (+330,453 bytes)
MinOpts (+17,921 bytes)
FullOpts (+312,532 bytes)
tpdiff: Diff JIT options: JitBypassAPXCheck=1 Overall (+0.27% to +0.60%)
MinOpts (+0.82% to +1.08%)
FullOpts (+0.22% to +0.38%)
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
3. JIT unit testsDOTNET_JitBypassAPXCheck = 0: DOTNET_JitBypassAPXCheck = 1: |
4. Supplement files:To see detail diffs, please refer to the following files: (files are too large to display on github) asm: tpdiff: |
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This was referenced Oct 23, 2024
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Update comments. Merge the REX2 changes into the original legacy emit path bug fix: Set REX2.W with correct mask code. register encoding and prefix emitting logics. Add REX2 prefix emit logic bug fixes Add Stress mode for REX2 encoding and some bug fixes resolve comments: 1. add assertion check for UD opcodes. 2. add checks for EGPRs. Add REX2 to emitOutputAM, and let LEA to be REX2 compatible. Add REX2.X encoding for SIB byte But fixes: add REX2 prefix on the path in RI where MOV is specially handled. Enable REX2 encoding for `movups` fixed bugs in REX2 prefix emitting logic when working with map 1 instructions, and enabled REX2 for POPCNT legacy map index-er bug fixes some clean-up Adding initial APX unit testing path. Adding a coredistools dll that has LLVM APX disasm capability. It must be coppied into a CORE_ROOT manually. clean up work for REX2 narrow the REX2 scope to `sub` only some clean up based on the comments. bug fix resolve comment
- SV path is mostly for debugging purposes Added encoding unit tests for instructions with immediates
Code refactoring: AddX86PrefixIfNeeded.
… missing in JIT, may indicate these instructions are not being used in JIT, drop them for now.
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1. make sure RWR_RRD_SHF has correct register update mode 2. make sure shift instructions will get correct opcode in RR path.
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Overview
This PR is built based on #106557, and is the first one that covers APX-EXTENDED-EVEX encoding.
This PR adds extended EVEX encoding for legacy instructions that are promoted to the EVEX encoding space, currently only instructions wit the new data destination (EVEX.NDD) feature, are covered in the PR. We plan to cover the encoding and instructions for flag suppression (EVEX.NF) in follow-up PRs.
Covered instructions:
Specification
EVEX extension of legacy instructions is one of the changes made on the original EVEX prefix to accommodate the ISA features and new instructions introduced by APX, and this part of extension focuses on promoting legacy instructions into EVEX encoding space and providing them with features like EGPR access, new data destination, zero upper, flag suppression.
As shown in the figure, some bits in original EVEX prefix have been re-purposed: EVEX.b to EVEX.ND, first bit of EVEX.aaa to EVEX.NF, and some bits have become reserved and has to be 0. Also, the promoted legacy instructions take a new legacy-map-index: map-4, as shown at EVEX.bits[18:16], say EVEX.mmm field, to be 100b.
All the promoted legacy instructions should follow this encoding schema, and for instructions that does not use these REX bits for access upper registers, these bits: EVEX.R4, X4, B4, R3, X3, B3 should be kept in logical-0 (0, or 1 if defined in inverted way.).
Design
As stated above, this PR will cover the encoding changes needed for EVEX extension for legacy instructions and support for EVEX.ND.
The bulk of the changes occur in the backend emitter, and some changes are added to code generation as the entry of optimization of NDD format.
One part I need to call out in the design is that we separated the EVEX encoding path for legacy instructions with the original EVEX path, and the new emit path will be guarded by
TakesApxExtendedEvexPrefix. The main reason for this is that the legacy extension part for APX-EVEX will break the assumption that EVEX is only for SIMD instructions and will only be appear on SIMD instruction emit paths, which JIT carries a lot of assertion check to verify. To let the original checks hold as much as possible, we finally chose to establish a stand-alone branch for extended legacy instructions on the path that does not have legacy encoding, or re-use the existing legacy encoding path with some prefix work.Optimization & Performance
In the asmdiff part below, code size regression was observed, say the use of EVEX.ND feature will increase the code size, in detail, the NDD form will introduce at most 2-byte regression per instruction, this is expected as we are using a 4-byte prefixed instruction to replace 2 legacy instructions which are normally 2 bytes. This creates the tradeoff between code size and instructions count, and we will be contributing to teach JIT how to wisely use this feature to get maximum performance gain while controlling the code size regression with a series of followed tuning works.
For better tuning the features, we added the optimization knob for NDD:
JitEnableAPXNDD, now NDD optimization is there for a few binary and unary instructions when the target register is different from src operands, but to use this feature more wisely, we will need more tunning work in the future, so we plan to have individual tunning knob for each feature APX provides, like NDD, NF, etc.Testing
Results separately posted below.
Follow-up plans
After this PR, we will continue to complete the APX-EVEX support for EVEX.NF for legacy/VEX instructions, and further APX-EVEX support for VEX/EVEX instructions.