JIT: Improve containment for widening intrinsics

[saucecontrol]

This adds containment support for the AVX-512 integer widening loads and fixes a few problems with the existing logic. In summary, it:

• Replaces a faulty calculation that prevented containment of full vector loads for some of the added AVX-512 instructions.
• Supports SIMD scalar load containment in more situations.
• Prevents containment in places it was previously allowed and shouldn't have been.

Examples:

Enabled containment of scalar loads for all qualifying widening instructions

Scalar load containment was previously disabled for all widening instructions except movddup.

static unsafe Vector128<short> ShouldContainScalarLoad(byte* ptr)
{
    return Sse41.ConvertToVector128Int16(Sse2.LoadScalarVector128((ulong*)ptr).AsByte());
}

Before

vmovq    xmm0, qword ptr [rdx]
vpmovzxbw xmm0, xmm0

After

vpmovzxbw xmm0, qword ptr [rdx]

Disabled containment of scalar loads smaller than the instruction requirement

Scalar load containment was enabled unconditionally for movddup. This example should not be contained because it reads only 4 bytes, while the contained load will read 8.

static unsafe Vector128<double> ShouldNotContainDdup(byte* ptr)
{
    return Sse3.MoveAndDuplicate(Sse.LoadScalarVector128((float*)ptr).AsDouble());
}

Before

vmovddup xmm0, qword ptr [rdx]

After

vmovss   xmm0, dword ptr [rdx]
vmovddup xmm0, xmm0

Disabled containment of aligned loads smaller than 16 bytes in MinOpts

In MinOpts, we typically allow containment of aligned loads on non-VEX hardware because the instructions will fault on unaligned addresses, however this is not true for instructions that load smaller values. This example was previously contained with MinOpts, EnableAVX=0.

static unsafe Vector128<short> ShouldNotContainAlignedLoad(byte* ptr)
{
    return Sse41.ConvertToVector128Int16(Sse2.LoadAlignedVector128(ptr));
}

Before

pmovzxbw xmm0, qword ptr [rax]

After

movdqa   xmm0, xmmword ptr [rax]
pmovzxbw xmm0, xmm0

Remaining diffs are all improvements.

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[saucecontrol]

These instructions are AVX+ so they imply VEX encoding.

[tannergooding]

CC. @dotnet/jit-contrib for secondary review.