Connect PMP/PMA excpetions

README.md

@@ -24,8 +24,7 @@ FRISCV is a SystemVerilog implementation of the [RISCV ISA](https://riscv.org):
 - Privilege modes:
     - Machine-mode only for simple embedded system
     - User-mode for secure embedded system
-- Physical memory protection (PMP)
-- Physical memory attribute (PMA)
+- Physical memory protection (PMP) & Physical Memory Attribute (PMA), up to 16 regions
 - External, software and timer interrupts
 - Support multiple (optional) extensions:
     - RV32I & RV32E architecture

doc/privilege.md

@@ -81,7 +81,11 @@ The privilege modes support have been designed based on RISC-V ISA specification
 - mcountinhibit: stop a specific counter
 - Machine Environment Configuration Registers (menvcfg and menvcfgh)
 
-## PMP
+## PMP / PMA
+
+To support secure processing and contain faults, it is desirable to limit the physical addresses
+accessible by software running on a hart. PMP violations are always trapped precisely at the
+processor.
 
 PMP checks are applied to all accesses whose effective privilege mode is S or U, including
 instruction fetches and data accesses in S and U mode, and data accesses in M-mode when the MPRV bit
@@ -177,6 +181,17 @@ to TOR, address 0x00 is the lower bound)
 
 [Sifive slides](https://cdn2.hubspot.net/hubfs/3020607/SiFive-RISCVCoreIP.pdf?t=1512606290763)
 
+
+Test:
+- read/execute instruction outside allowed regions (U-mode)
+- read/write data in U-mode
+- read/write data in M-mode with MPRV + MPP w/ U-mode
+    -> Store = store access-fault
+    -> Load = load access-fault
+    -> Execute = instruction access-fault
+- all region configuration mode
+
+
 ## Interrupts
 
 - WFI:

doc/project_mgt_hw.md

@@ -97,7 +97,7 @@ Any new features should be carefully study to ensure a proper exception and inte
 - [ ] Out of order support in AXI (memfy if not using cache)
 
 
-## Control
+## Control / CSR
 
 - [ ] Detect IO requests to forward info for FENCE execution
 - [ ] Branch prediction
@@ -107,6 +107,7 @@ Any new features should be carefully study to ensure a proper exception and inte
     - [ ] https://github.com/tommythorn/yarvi/blob/master/rtl/yarvi.v#L184
     - [ ] https://danluu.com/branch-prediction
 - [ ] Rewind pipeline (L0 local cache)
+- [ ] Pipeline PMP CSR up to MPU setup path and stop the core with csr_ready during few cycles
 
 
 ## Processing
@@ -115,7 +116,7 @@ Any new features should be carefully study to ensure a proper exception and inte
 - [ ] Memfy:
     - If not ready, and request present, the FSM can’t drive further data
     - Manage RRESP/BRESP in the exception bus
-- [ ] Support F extension
+- [ ] Support F extension: https://bellard.org/softfp/
 - [ ] Division
     - [ ] Save bandwidth by removing dead cycles
     - [ ] Manage pow2 division by shifting
@@ -163,6 +164,8 @@ Any new features should be carefully study to ensure a proper exception and inte
 
 # Ideas / Applications
 
+- [ ] Include a DMA in platform
+    - must respect PMP / PMA
 - [ ] Next CPU architecture:
     - Super scalar architecture
         - https://en.m.wikipedia.org/wiki/Instruction-level_parallelism

doc/project_mgt_sw.md

@@ -9,13 +9,13 @@
         - [ ] https://github.com/ssloy/tinyraytracer
     - [ ] Type conversion
     - [ ] Image resizer
-	- [ ] Generate images with lines, triangles, ray tracing… 24fps
-		- [ ] https://github.com/ssloy/tinyrenderer/wiki/Lesson-2:-Triangle-rasterization-and-back-face-culling
-		- [ ] https://gabrielgambetta.com/computer-graphics-from-scratch/07-filled-triangles.html
-		- [ ] https://github.com/OscarSaharoy/ascii-raytrace
-		- [ ] https://fabiensanglard.net/another_world_polygons/
-	- [ ] Hash table https://github.com/PerformanC/tablec/tree/closed-addressing
-	- [ ] CoreMark https://github.com/eembc/coremark
+    - [ ] Generate images with lines, triangles, ray tracing… 24fps
+        - [ ] https://github.com/ssloy/tinyrenderer/wiki/Lesson-2:-Triangle-rasterization-and-back-face-culling
+        - [ ] https://gabrielgambetta.com/computer-graphics-from-scratch/07-filled-triangles.html
+        - [ ] https://github.com/OscarSaharoy/ascii-raytrace
+        - [ ] https://fabiensanglard.net/another_world_polygons/
+    - [ ] Hash table https://github.com/PerformanC/tablec/tree/closed-addressing
+    - [ ] CoreMark https://github.com/eembc/coremark
 
 # BACKLOG
 
@@ -65,7 +65,11 @@ Minimalistic Unix
 
 # Ideas / Applications
 
-- [ ] Support Linux / FreeBSD / NetBSD: https://github.com/cnlohr/mini-rv32ima
+- [ ] Try https://github.com/berry-lang/berry
+- [ ] Try
+- [ ] Support Linux / FreeBSD / NetBSD
+    - https://github.com/cnlohr/mini-rv32ima
+    - https://popovicu.com/posts/789-kb-linux-without-mmu-riscv/
 - [ ] Code Pong with AI for auto game
 - [ ] Run Doom: https://www.youtube.com/watch?v=uZMNK17VCMU&list=WL&index=1&t=2s
 - [ ] Code the game of life
@@ -86,7 +90,8 @@ Minimalistic Unix
     - Able to update the FPGA bitstream with the new program
 - [ ] Implement a neural network with the processor and TF lite
 - [ ] Retro gaming platform
-
+- [ ] Try Rust
+    - https://popovicu.com/posts/bare-metal-rust-risc-v-with-dynamic-memory/
 DONE:
 
 - [X] Pool arena / malloc-free / integrated in benchmark

rtl/friscv_control.sv

@@ -73,7 +73,7 @@ module friscv_control
         input  wire                       proc_ready,
         output logic [`INST_BUS_W   -1:0] proc_instbus,
         input  wire  [4             -1:0] proc_fenceinfo,
-        input  wire  [2             -1:0] proc_exceptions,
+        input  wire  [`PROC_EXP_W   -1:0] proc_exceptions,
         input  wire                       proc_busy,
         // interface to activate teh CSR management
         output logic                      csr_en,
@@ -90,8 +90,8 @@ module friscv_control
         output logic [5             -1:0] ctrl_rd_addr,
         output logic [XLEN          -1:0] ctrl_rd_val,
         // PMP / PMA Check
-        output logic [AXI_ADDR_W    -1:0] pmp_addr,
-        input  wire  [4             -1:0] pmp_allow,
+        output logic [AXI_ADDR_W    -1:0] mpu_addr,
+        input  wire  [4             -1:0] mpu_allow,
         // CSR shared bus
         input  wire  [`CSR_SB_W     -1:0] csr_sb,
         output logic [`CTRL_SB_W    -1:0] ctrl_sb
@@ -211,14 +211,21 @@ module friscv_control
     logic [XLEN       -1:0] mtval_info;
     logic                   load_misaligned;
     logic                   store_misaligned;
+    logic                   inst_access_fault;
     logic                   illegal_instruction;
-    logic                   wfi_not_allowed;
+    logic                   wfi_tw;
     logic                   trap_occuring;
     logic                   sync_trap_occuring;
     logic                   async_trap_occuring;
     logic                   ecall_umode;
     logic                   ecall_mmode;
     logic [2          -1:0] priv_mode;
+    logic                   load_access_fault;
+    logic                   store_access_fault;
+
+    logic [`EXP_INST_W-1:0] exp_inst;
+    logic [`EXP_ADDR_W-1:0] exp_addr;
+    logic [`EXP_PC_W  -1:0] exp_pc;
 
     // Logger setup
     `ifdef USE_SVL
@@ -462,17 +469,19 @@ module friscv_control
 
     assign csr_en = inst_ready && sys[`IS_CSR] & (cfsm==FETCH) & !proc_busy;
 
-    assign proc_instbus[`OPCODE +: `OPCODE_W] = opcode;
-    assign proc_instbus[`FUNCT3 +: `FUNCT3_W] = funct3;
-    assign proc_instbus[`FUNCT7 +: `FUNCT7_W] = funct7;
-    assign proc_instbus[`RS1    +: `RS1_W   ] = rs1   ;
-    assign proc_instbus[`RS2    +: `RS2_W   ] = rs2   ;
-    assign proc_instbus[`RD     +: `RD_W    ] = rd    ;
-    assign proc_instbus[`ZIMM   +: `ZIMM_W  ] = zimm  ;
-    assign proc_instbus[`IMM12  +: `IMM12_W ] = imm12 ;
-    assign proc_instbus[`IMM20  +: `IMM20_W ] = imm20 ;
-    assign proc_instbus[`CSR    +: `CSR_W   ] = csr   ;
-    assign proc_instbus[`SHAMT  +: `SHAMT_W ] = shamt ;
+    assign proc_instbus[`OPCODE   +: `OPCODE_W ] = opcode;
+    assign proc_instbus[`FUNCT3   +: `FUNCT3_W ] = funct3;
+    assign proc_instbus[`FUNCT7   +: `FUNCT7_W ] = funct7;
+    assign proc_instbus[`RS1      +: `RS1_W    ] = rs1   ;
+    assign proc_instbus[`RS2      +: `RS2_W    ] = rs2   ;
+    assign proc_instbus[`RD       +: `RD_W     ] = rd    ;
+    assign proc_instbus[`ZIMM     +: `ZIMM_W   ] = zimm  ;
+    assign proc_instbus[`IMM12    +: `IMM12_W  ] = imm12 ;
+    assign proc_instbus[`IMM20    +: `IMM20_W  ] = imm20 ;
+    assign proc_instbus[`CSR      +: `CSR_W    ] = csr   ;
+    assign proc_instbus[`SHAMT    +: `SHAMT_W  ] = shamt ;
+    assign proc_instbus[`INST     +: `INST_W   ] = instruction;
+    assign proc_instbus[`PC       +: `PC_W     ] = pc_reg;
 
     assign csr_instbus = proc_instbus;
 
@@ -561,7 +570,7 @@ module friscv_control
 
     assign pc_val = pc_reg;
 
-    assign pmp_addr = pc_reg;
+    assign mpu_addr = pc_reg;
 
     assign flush_reqs = flush_pipe;
 
@@ -1022,6 +1031,7 @@ module friscv_control
     //
     // ISA registers write stage
     //
+    //(inst_access_fault)    ? exp_pc      :
     ///////////////////////////////////////////////////////////////////////////
 
     // register source 1 & 2 read
@@ -1148,20 +1158,31 @@ module friscv_control
     // illegal instruction exception. An implementation may have WFI always raise an illegal instruction
     // exception in less-privileged modes when TW=1, even if there are pending globally-disabled interrupts
     // when the instruction is executed. TW is read-only 0 when there are no modes less privileged than M.
-    assign wfi_not_allowed = 1'b0;
-
-    assign load_misaligned = proc_exceptions[`LD_MA];
-    assign store_misaligned = proc_exceptions[`ST_MA];
+    assign wfi_tw = 1'b0;
 
     assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready;
 
+    assign inst_access_fault = (!mpu_allow[`PMA_X] | !mpu_allow[`PMA_R]) & (priv_mode == `UMODE);
+
+    assign load_misaligned = proc_exceptions[`LDMA];
+
+    assign store_misaligned = proc_exceptions[`STMA];
+
+    assign load_access_fault = proc_exceptions[`LAF];
+
+    assign store_access_fault = proc_exceptions[`SAF];
+
+    assign exp_pc = proc_exceptions[`EXP_PC +: `EXP_PC_W];
+
+    assign exp_inst = proc_exceptions[`EXP_INST +: `EXP_INST_W];
+
+    assign exp_addr = proc_exceptions[`EXP_ADDR +: `EXP_ADDR_W];
+
     generate
     if (USER_MODE) begin: UMODE_EXPEC
         assign illegal_instruction = (priv_mode==`MMODE)                 ? '0         :
                                      (sys[`IS_MRET])                     ? inst_ready :
                                      (sys[`IS_CSR] && csr[9:8] != 2'b00) ? inst_ready :
-                                     // Check if WFI must be trapped or not
-                                     // (sys[`IS_WFI] )                     ? inst_ready :
                                                                            '0;
     end else begin : NO_UMODE
         assign illegal_instruction = '0;
@@ -1213,6 +1234,9 @@ module friscv_control
     //           |  3               |   Environment break
     //           |  3               |   Load/Store/AMO address breakpoint
     // ------------------------------------------------------------------------
+    //           |  5               |   Load access fault
+    //           |  7               |   Store access fault
+    // ------------------------------------------------------------------------
     //           |  6               |   Store/AMO address misaligned
     //           |  4               |   Load address misaligned
     // ------------------------------------------------------------------------
@@ -1231,21 +1255,27 @@ module friscv_control
                          (sb_mtip)              ? {1'b1, {XLEN-5{1'b0}}, 4'h7} :
                          (sb_meip)              ? {1'b1, {XLEN-5{1'b0}}, 4'hB} :
                          // then follow sync exceptions
+                         (inst_access_fault)    ? {{XLEN-4{1'b0}}, 4'h1}  :
                          (illegal_instruction)  ? {{XLEN-4{1'b0}}, 4'h2}  :
                          (csr_ro_wr)            ? {{XLEN-4{1'b0}}, 4'h2}  :
                          (inst_addr_misaligned) ? '0                      :
                          (ecall_umode)          ? {{XLEN-4{1'b0}}, 4'h8}  :
                          (ecall_mmode)          ? {{XLEN-4{1'b0}}, 4'hB}  :
                          (sys[`IS_EBREAK])      ? {{XLEN-4{1'b0}}, 4'h3}  :
-                         (store_misaligned)     ? {{XLEN-4{1'b0}}, 4'h6}  :
+                         (load_access_fault)    ? {{XLEN-4{1'b0}}, 4'h5}  :
+                         (store_access_fault)   ? {{XLEN-4{1'b0}}, 4'h7}  :
                          (load_misaligned)      ? {{XLEN-4{1'b0}}, 4'h4}  :
+                         (store_misaligned)     ? {{XLEN-4{1'b0}}, 4'h6}  :
                          (inst_dec_error)       ? {{XLEN-5{1'b0}}, 5'h18} :
                                                   '0;
 
     // MTVAL: exception-specific information
     assign mtval_info = (inst_dec_error)       ? instruction :
-                        (wfi_not_allowed)      ? instruction :
+                        (wfi_tw)               ? instruction :
                         (illegal_instruction)  ? instruction :
+                        (inst_access_fault)    ? pc_reg      :
+                        (load_access_fault)    ? exp_pc      :
+                        (store_access_fault)   ? exp_pc      :
                         (inst_dec_error)       ? instruction :
                         (csr_ro_wr)            ? instruction :
                         (inst_addr_misaligned) ? pc_reg      :
@@ -1262,6 +1292,9 @@ module friscv_control
                                 load_misaligned      |
                                 illegal_instruction  |
                                 store_misaligned     |
+                                inst_access_fault    |
+                                load_access_fault    |
+                                store_access_fault   |
                                 inst_dec_error       ;
 
     assign trap_occuring = async_trap_occuring | sync_trap_occuring;

rtl/friscv_debug_h.sv

@@ -4,37 +4,37 @@
 `ifndef FRISCV_DEBUG
 `define FRISCV_DEBUG
 
-`define PC   0
-`define X1   1
-`define X2   2
-`define X3   3
-`define X4   4
-`define X5   5
-`define X6   6
-`define X7   7
-`define X8   8
-`define X9   9
-`define X10  10
-`define X11  11
-`define X12  12
-`define X13  13
-`define X14  14
-`define X15  15
-`define X16  16
-`define X17  17
-`define X18  18
-`define X19  19
-`define X20  20
-`define X21  21
-`define X22  22
-`define X23  23
-`define X24  24
-`define X25  25
-`define X26  26
-`define X27  27
-`define X28  28
-`define X29  29
-`define X30  30
-`define X31  31
+`define DBG_PC   0
+`define DBG_X1   1
+`define DBG_X2   2
+`define DBG_X3   3
+`define DBG_X4   4
+`define DBG_X5   5
+`define DBG_X6   6
+`define DBG_X7   7
+`define DBG_X8   8
+`define DBG_X9   9
+`define DBG_X10  10
+`define DBG_X11  11
+`define DBG_X12  12
+`define DBG_X13  13
+`define DBG_X14  14
+`define DBG_X15  15
+`define DBG_X16  16
+`define DBG_X17  17
+`define DBG_X18  18
+`define DBG_X19  19
+`define DBG_X20  20
+`define DBG_X21  21
+`define DBG_X22  22
+`define DBG_X23  23
+`define DBG_X24  24
+`define DBG_X25  25
+`define DBG_X26  26
+`define DBG_X27  27
+`define DBG_X28  28
+`define DBG_X29  29
+`define DBG_X30  30
+`define DBG_X31  31
 
 `endif