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Change: update REPL app to use config file
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dpretet committed Nov 21, 2023
1 parent 8f3bdc3 commit 9ef343f
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Showing 5 changed files with 32 additions and 5 deletions.
7 changes: 6 additions & 1 deletion doc/TODO.md
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,8 @@
- [X] if MIE/SIE=0, wait for any intp and move forward
- [X] Support MSTATUS.TW (timeout platform-dependent)
- [X] add FIFO for memory exceptions
- [ ] mcounteren: accessibility to lower privilege modes
- [X] Drive aprot[0] based on priviledge mode
- [X] mcounteren: accessibility to lower privilege modes
- Bit x = 1, lower privilege mode can read the counter
- Bit x = 0, lower privilege mode access is forbidden and raise an illegal instruction exception

Expand Down Expand Up @@ -58,6 +59,10 @@ MPU:
- [X] execute in M-mode without X + locked region
- [X] locked access to change configuration

MCOUNTER:
- Bit x = 1, lower privilege mode can read the counter
- Bit x = 0, lower privilege mode access is forbidden and raise an illegal instruction exception

Final:
- Pass compliance with U-mode
- Run REPL app
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12 changes: 12 additions & 0 deletions rtl/friscv_control.sv
Original file line number Diff line number Diff line change
Expand Up @@ -752,7 +752,9 @@ module friscv_control
if (jalr | branching) begin

if (!cant_jump) begin
`ifdef USE_SVL
print_instruction;
`endif
pc_reg <= pc;
end

Expand All @@ -773,7 +775,9 @@ module friscv_control
log.info("JAL");
`endif

`ifdef USE_SVL
print_instruction;
`endif
pc_reg <= pc;
flush_pipe <= 1'b1;

Expand Down Expand Up @@ -844,28 +848,36 @@ module friscv_control

// CSR instructions
end else if (sys[`IS_CSR] && !cant_sys) begin
`ifdef USE_SVL
print_instruction;
`endif
flush_pipe <= 1'b0;
pc_reg <= pc;

// FENCE instruction (not supported)
end else if (!proc_busy && csr_ready) begin
`ifdef USE_SVL
print_instruction;
`endif
flush_pipe <= 1'b0;
pc_reg <= pc;
end

// LUI and AUIPC execution, done in this module
end else if (lui_auipc && !cant_lui_auipc) begin
`ifdef USE_SVL
print_instruction;
`endif
flush_pipe <= 1'b0;
pc_reg <= pc;

// All other instructions
end else if (processing) begin

if (!cant_process) begin
`ifdef USE_SVL
print_instruction;
`endif
flush_pipe <= 1'b0;
pc_reg <= pc;
end
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8 changes: 8 additions & 0 deletions test/apps/config.cfg
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
XLEN,32
CACHE_EN,1
CACHE_BLOCK_W,128
GEN_EIRQ,0
ERROR_STATUS_X31,1
USER_MODE,0
CONTROL_VERBOSITY,0
CONTROL_ROUTE,2
8 changes: 5 additions & 3 deletions test/apps/run.sh
Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,16 @@ set -e
# Variables and setup
#------------------------------------------------------------------------------

cfg_file="config.cfg"

# Disable runtime timeout check for this testbench
TIMEOUT=0

# Minumum value the program counter should reach in bytes
MIN_PC=65692

# Don't drop VCD, to avoid storing GB of raw data
NO_VCD=1
NO_VCD=0

# Enable UART link to the processor (platform only)
INTERACTIVE=1
Expand Down Expand Up @@ -96,11 +98,11 @@ main() {

# If user specified a testcase, or a testsuite, use it
if [[ -n $TC ]]; then
run_testsuite "$TC"
run_testsuite "$TC" "$cfg_file"
# Else run all the supported testsuite
else
# Execute the testsuites
run_testsuite "./tests/*.v"
run_testsuite "./tests/*.v" "$cfg_file"
fi

# OK, sounds good, exit gently
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2 changes: 1 addition & 1 deletion test/common/functions.sh
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ read_config() {
cen=0 # cache enable
cw=32 # cache width

DEFINES="FRISV_SIM=1;USE_SVL=1;"
DEFINES="FRISV_SIM=1;USE_SVL=0;"

while IFS=, read -r name value; do
DEFINES="${DEFINES}${name}=${value};"
Expand Down

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