Not finished yet: Modify code to match RANC functionality

verilog/neuron_core_256x256/AddressDecoder_256x256.v

@@ -1,26 +1,56 @@
+/*
+ * Memory Mapping
+ * Address Range                | Address[15:14] | Description
+ * -----------------------------------------------------
+ * 0x30000000 - 0x30001FFF      | 00            | Synapse matrix
+ * Memory region for synapse matrix configuration.
+ *
+ * 0x30004000 - 0x30004FFF      | 01            | Neuron Parameters
+ * Region for setting neuron parameters.
+ * Address[11:4] Decoding for determining the neuron index of parameter
+ *
+ * 0x30008000 - 0x30008003      | 10            | Neuron spike out
+ * Output for neuron spike events.
+ *
+ * 0x3000C000 - 0x3000C003      | 11            | Spike events
+ * Memory region for logging spike events.
+ * Address[1:0] Decoding for Spike Events:
+ * 00: synap_matrix_select = 1
+ * 01: param_select = 1
+ * 10: neuron_spike_out_select = 1
+ * 11: last_event_spike = 1
+ */
 module AddressDecoder_256x256 (
     input [31:0] addr,
     output reg synap_matrix,
-    output reg [4:0] param_num,   // Will be valid only if address is in param range
+    output reg param,
+    output reg [7:0] param_num,   // Will be valid only if address is in param range
     output reg neuron_spike_out,
-    output reg param
+    output reg new_image_packet,
+    output reg last_image_packet
 );
 
     always @(addr) begin
         // Default outputs to 0
         synap_matrix = 0;
         param = 0;
-        param_num = 5'b0;
+        param_num = 7'b0;
         neuron_spike_out = 0;
+        new_image_packet = 0;
+        last_image_packet = 0;
 
-        // Decode based on addr[14:13]
-        case(addr[14:13])
+        // MODIFIED: Decode based on addr[15:14], not addr[14:13]!
+        case(addr[15:14])
             2'b00: synap_matrix = 1;
             2'b01: begin
                 param = 1;
                 param_num = addr[11:4]; // Param num takes 8 bit to represent 256 params
             end
             2'b10: neuron_spike_out = 1;
+            2'b11: begin 
+                new_image_packet = addr[0];
+                last_image_packet = addr[1];
+            end
             default: ; // Do nothing, outputs remain 0
         endcase
     end

verilog/neuron_core_256x256/neuron_block_256x256.v

@@ -1,6 +1,4 @@
 module neuron_block_256x256 (
-    input clk,
-    input rst,
     input signed [7:0] voltage_potential_i, // Current voltage potential
     input signed [7:0] pos_threshold_i,     // Positive threshold
     input signed [7:0] neg_threshold_i,     // Negative threshold
@@ -14,25 +12,13 @@ module neuron_block_256x256 (
     input signed [7:0] neg_reset_i,         // Negative reset
     input enable_i,                  // Enable signal
     output reg signed [7:0] new_potential_o, // New voltage potential - changed to reg
-    output reg spike_o               // Spike output (1-bit) - changed to reg
+    output reg spike_o,               // Spike output (1-bit) - changed to reg
+    input new_image_packet_i,         // signal to indicate new image packet
+    input last_image_packet_i         // signal to indicate last image packet
 );
-    reg [7:0] count,
     reg [7:0] selected_weight;
     reg [8:0] potential_calc; // changed to reg
 
-    // Update count a.k.a 
-    always @(posedge clk or negedge reset_n) begin
-        if (rst) begin
-            count <= 0;
-        end else begin
-            if (count == 8'hFF) begin
-                count <= 0;
-            end else begin
-                count <= count + 1;
-            end
-        end
-    end
-
     // Adjusted Weight selection
     always @(*) begin
         case(weight_select_i)
@@ -44,13 +30,13 @@ module neuron_block_256x256 (
         endcase
     end
 
-    // Modified neuron block logic: Add a count signal to check: Only after iterating through all 256 axons, the new_potential_o and spike_o are updated  
-    always @(count) begin       
-        if (enable_i == 1) begin
-            if (count == 0) begin 
-                potential_calc = {1'b0, voltage_potential_i};
-            end 
-            else if (count == 255) begin 
+    // Modified neuron block logic: Add signals to check for new_image_spike and last_image_spike
+    always @(*) begin
+        if (new_image_packet_i) begin 
+            potential_calc = {1'b0, voltage_potential_i};
+        end       
+        else if (enable_i) begin             
+            if (last_image_packet_i) begin 
                 // Calculate potential
                 potential_calc = potential_calc + selected_weight + leak_value_i; // Modified based on Mr.Vu's code: + (not -) leak_value
 
@@ -73,7 +59,8 @@ module neuron_block_256x256 (
             else begin 
                 potential_calc = potential_calc + selected_weight;
             end
-        end else begin
+        end 
+        else begin
             new_potential_o = 8'b0;
             spike_o = 0;
         end

verilog/neuron_core_256x256/neuron_core_256x256.v

@@ -1,3 +1,12 @@
+/* TODO: Signal first packet and last packet of an image
+
+Approach 1: Have a pseudo block in memory mapping (32’b3000Cxxx ⇒ addr[15:14] = 2’b11),
+            storing 1 event new_image_spike + 1 num_spikes value) 
+            & Create a new module Controller to store controller states 
+            new_image_spike, process_image_spike, last_image_spike, process_last_spike
+Approach 2: Try logic analyzer to control new_image_packet and last_image_packet
+
+*/
 module neuron_core_256x256
 (
     `ifdef USE_POWER_PINS
@@ -28,12 +37,20 @@ wire synap_matrix_select;               // Active when synapse matrix is the tar
 wire param_select;                      // Active when any neuron parameter is the target
 wire [7:0] param_num;                   // Specifies the specific neuron parameter targeted
 wire neuron_spike_out_select;           // Active when neuron spike out is the target
-
+wire new_image_packet, last_image_packet; // Signals to indicate new and last image packets
 
 wire [255:0] neurons_connections;
 wire [255:0] spike_out;
 wire external_write_en;
 
+/*
+* Each 32-bit entry in the slave_dat_o array corresponds to wbs_dat_o from a sub-module
+* Since slave_dat_o is only `wire` => it main use is to combine with circuit to wire matching wbs_dat_o signals 
+of submodule to wbs_dat_o of the top module 
+*/
+wire [31:0] slave_dat_o [257:0];        // Data outputs from each of the 258 memory blocks
+wire [257:0] slave_ack_o;               // Acknowledgment signals from each memory block
+
 /* 
 * AddressDecoder_256x256: Decodes the incoming address from the Wishbone
 * interface (wbs_adr_i) and determines the target memory block among the 258 blocks
@@ -46,15 +63,11 @@ AddressDecoder_256x256 addr_decoder (
     .synap_matrix(synap_matrix_select),
     .param(param_select),
     .param_num(param_num),
-    .neuron_spike_out(neuron_spike_out_select)
+    .neuron_spike_out(neuron_spike_out_select),
+    .new_image_packet(new_image_packet),
+    .last_image_packet(last_image_packet)
 );
-/*
-* Each 32-bit entry in the slave_dat_o array corresponds to wbs_dat_o from a sub-module
-* Since slave_dat_o is only `wire` => it main use is to combine with circuit to wire matching wbs_dat_o signals 
-of submodule to wbs_dat_o of the top module 
-*/
-wire [31:0] slave_dat_o [257:0];        // Data outputs from each of the 258 memory blocks
-wire [257:0] slave_ack_o;               // Acknowledgment signals from each memory block
+
 
 synapse_matrix_256x256 #(.BASE_ADDR(SYNAPSE_BASE)) sm (
     .wb_clk_i(clk),
@@ -74,10 +87,11 @@ generate
     genvar i;
     for (i = 0; i < 256; i = i + 1) begin : neuron_instances
         // wires for interfacing neuron_parameters and neuron_block
-        wire [7:0] voltage_potential, pos_threshold, neg_threshold, leak_value;
-        wire [7:0] weight_type1, weight_type2, weight_type3, weight_type4;
-        wire [7:0] weight_select, pos_reset, neg_reset;
-        wire [7:0] new_potential;
+        wire signed [7:0] voltage_potential, pos_threshold, neg_threshold, leak_value;
+        wire signed [7:0] weight_type1, weight_type2, weight_type3, weight_type4;
+        wire signed [7:0] pos_reset, neg_reset;
+        wire [7:0] weight_select;
+        wire signed [7:0] new_potential;
 
         neuron_parameters_256x256 #(.BASE_ADDR(PARAM_BASE + i*PADDING_PARAM)) np_inst (
             .wb_clk_i(clk),
@@ -119,9 +133,9 @@ generate
             .neg_reset_i(neg_reset),
             .new_potential_o(new_potential),
             .enable_i(neurons_connections[i]),
-            .spike_o(spike_out[i])
-            .clk(clk),
-            .rst(rst)
+            .spike_o(spike_out[i]),
+            .new_image_packet_i(new_image_packet),
+            .last_image_packet_i(last_image_packet)
         );
     end
 endgenerate