Add logic analyzer signals to send new_image_spike and last_image_spi…

…ke concurrently with input spikes

verification/tb_neuron_core_256x256/tb_neuron_core_256x256.sv

@@ -19,6 +19,16 @@ logic [31:0] wbs_dat_i;
 wire wbs_ack_o;
 wire [31:0] wbs_dat_o;
 
+logic new_image_packet, last_image_packet; // Signals to indicate new and last image packets
+
+// Logic Analyzer Signals
+logic   [127:0] la_data_in,
+logic   [127:0] la_data_out,
+logic   [127:0] la_oenb // active-low, enable output from user_project_wrapper to managementSoC
+
+// Enable first 2 bits of LA signals for: new_image_packet & last_image_packet
+assign la_data_in[1:0] = {last_image_packet, new_image_packet};
+
 // Instantiate the Unit Under Test (UUT)
 neuron_core_256x256 uut_neuron_core (
     .clk(clk),
@@ -30,7 +40,10 @@ neuron_core_256x256 uut_neuron_core (
     .wbs_adr_i(wbs_adr_i),
     .wbs_dat_i(wbs_dat_i),
     .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o)
+    .wbs_dat_o(wbs_dat_o),
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb(la_oenb)
 );
 
 // Clock generation
@@ -115,7 +128,7 @@ logic [79:0] current_neuron_param;
 ////////////////////////////////////////////////////////////////
 event synap_matrix_start, synap_matrix_done; 
 event neuron_params_start, neuron_params_done;
-event new_image_packet, last_image_packet;
+event new_image_packet_event, last_image_packet_event;
 
 // Initial block for reset and tests
 initial begin //initial begin MUST NOT include initialization statements
@@ -169,13 +182,13 @@ initial begin //initial begin MUST NOT include initialization statements
 
     // end
     // Test by sending packets of 1st image
-    #20 -> new_image_packet;
-    wishbone_read(32'h3000C001); // new_image_packet = 1
+    #20 -> new_image_packet_event;
+    new_image_packet = 1; // new_image_packet = 1
     for (int j = 0; j < num_pic[0]; j++) begin
         wishbone_read(32'h30000000 + packet[j]*32); // Each synap connection of a neuron takes up 32 memory locations
     end
-    wishbone_read(32'h3000C003); // last_image_packet = 1
-    -> last_image_packet;
+    last_image_packet = 1; // last_image_packet = 1
+    -> last_image_packet_event;
 
 
     // Complete the test

verilog/neuron_core_256x256/AddressDecoder_256x256.v

@@ -12,22 +12,13 @@
  * 0x30008000 - 0x30008003      | 10            | Neuron spike out
  * Output for neuron spike events.
  *
- * 0x3000C000 - 0x3000C003      | 11            | Spike events
- * Memory region for logging spike events.
- * Address[1:0] Decoding for Spike Events:
- * 00: synap_matrix_select = 1
- * 01: param_select = 1
- * 10: neuron_spike_out_select = 1
- * 11: last_event_spike = 1
  */
 module AddressDecoder_256x256 (
     input [31:0] addr,
     output reg synap_matrix,
     output reg param,
     output reg [7:0] param_num,   // Will be valid only if address is in param range
-    output reg neuron_spike_out,
-    output reg new_image_packet,
-    output reg last_image_packet
+    output reg neuron_spike_out
 );
 
     always @(addr) begin
@@ -36,8 +27,6 @@ module AddressDecoder_256x256 (
         param = 0;
         param_num = 7'b0;
         neuron_spike_out = 0;
-        new_image_packet = 0;
-        last_image_packet = 0;
 
         // MODIFIED: Decode based on addr[15:14], not addr[14:13]!
         case(addr[15:14])
@@ -47,10 +36,6 @@ module AddressDecoder_256x256 (
                 param_num = addr[11:4]; // Param num takes 8 bit to represent 256 params
             end
             2'b10: neuron_spike_out = 1;
-            2'b11: begin 
-                new_image_packet = addr[0];
-                last_image_packet = addr[1];
-            end
             default: ; // Do nothing, outputs remain 0
         endcase
     end

verilog/neuron_core_256x256/neuron_block_256x256.v

@@ -32,11 +32,11 @@ module neuron_block_256x256 (
 
     // Modified neuron block logic: Add signals to check for new_image_spike and last_image_spike
     always @(*) begin
-        if (new_image_packet_i) begin 
-            potential_calc = {1'b0, voltage_potential_i};
-        end       
-        else if (enable_i) begin             
-            if (last_image_packet_i) begin 
+        if (enable_i) begin
+            if (new_image_packet_i) begin 
+                potential_calc = voltage_potential_i + selected_weight;
+            end                            
+            else if (last_image_packet_i) begin 
                 // Calculate potential
                 potential_calc = potential_calc + selected_weight + leak_value_i; // Modified based on Mr.Vu's code: + (not -) leak_value
 

verilog/neuron_core_256x256/neuron_core_256x256.v

@@ -26,6 +26,11 @@ module neuron_core_256x256
     input  wire [31:0] wbs_dat_i,
     output wire wbs_ack_o,
     output wire [31:0] wbs_dat_o
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb // active-low, enable output from user_project_wrapper to managementSoC
 );
 
 parameter SYNAPSE_BASE = 32'h30000000;  // Base address for Synapse Matrix
@@ -51,6 +56,10 @@ of submodule to wbs_dat_o of the top module
 wire [31:0] slave_dat_o [257:0];        // Data outputs from each of the 258 memory blocks
 wire [257:0] slave_ack_o;               // Acknowledgment signals from each memory block
 
+// Enable first 2 bits of LA signals for: new_image_spike & last_image_spike
+assign {last_image_packet, new_image_packet} = la_data_in[1:0];
+// assign la_write = ~la_oenb[1:0]
+
 /* 
 * AddressDecoder_256x256: Decodes the incoming address from the Wishbone
 * interface (wbs_adr_i) and determines the target memory block among the 258 blocks
@@ -63,9 +72,7 @@ AddressDecoder_256x256 addr_decoder (
     .synap_matrix(synap_matrix_select),
     .param(param_select),
     .param_num(param_num),
-    .neuron_spike_out(neuron_spike_out_select),
-    .new_image_packet(new_image_packet),
-    .last_image_packet(last_image_packet)
+    .neuron_spike_out(neuron_spike_out_select)
 );