Silicon/RK3588: Remove own NvStorage PCDs

Use gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorage* everywhere for consistency. This also fixes FTW, since its PCDs were previously set to wrong addresses in the DSC. Signed-off-by: Mario Bălănică <[email protected]>
edk2-porting · Jan 10, 2024 · 601a81a · 601a81a
1 parent 526d9e9
commit 601a81a
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Showing 7 changed files with 9 additions and 19 deletions.
diff --git a/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c b/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c
@@ -1010,7 +1010,7 @@ FvbConfigureFlashInstance (
   FtwSpareSize = PcdGet32 (PcdFlashNvStorageFtwSpareSize);
 
   FlashInstance->FvbSize = VariableSize + FtwWorkingSize + FtwSpareSize;
-  FlashInstance->FvbOffset = PcdGet32 (PcdNvStorageVariableBase);
+  FlashInstance->FvbOffset = PcdGet64 (PcdFlashNvStorageVariableBase64);
 
   FlashInstance->Media.MediaId = 0;
   FlashInstance->Media.BlockSize = SIZE_4KB;//FlashInstance->SpiDevice.Info->SectorSize;

diff --git a/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf b/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
@@ -67,9 +67,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-#  gRockchipTokenSpaceGuid.PcdSpiMemoryBase
-#  gRockchipTokenSpaceGuid.PcdSpiMemoryMapped
-  gRockchipTokenSpaceGuid.PcdNvStorageVariableBase
   gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash
   gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress
   gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress

diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
@@ -52,7 +52,7 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
   gArmTokenSpaceGuid.PcdArmPrimaryCore
   gArmTokenSpaceGuid.PcdFdSize
-  gRockchipTokenSpaceGuid.PcdNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize

diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Mem.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Mem.c
@@ -26,7 +26,7 @@ STATIC UINT64 mSystemMemorySize = FixedPcdGet64 (PcdSystemMemorySize);
 STATIC BOOLEAN                     VirtualMemoryInfoInitialized = FALSE;
 STATIC RK3588_MEMORY_REGION_INFO   VirtualMemoryInfo[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
 
-#define VariablesBase FixedPcdGet64(PcdNvStorageVariableBase)
+#define VariablesBase FixedPcdGet64(PcdFlashNvStorageVariableBase64)
 
 #define VariablesSize (FixedPcdGet32(PcdFlashNvStorageVariableSize)   + \
                        FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) + \
@@ -137,7 +137,7 @@ ArmPlatformGetVirtualMemoryMap (
     VirtualMemoryInfo[Index].Type             = RK3588_MEM_RESERVED_REGION;
     VirtualMemoryInfo[Index++].Name           = L"BAD2";
   }
-  
+
   // Firmware Volume
   // VirtualMemoryTable[Index].PhysicalBase    = FixedPcdGet64 (PcdFdBaseAddress);
   // VirtualMemoryTable[Index].VirtualBase     = VirtualMemoryTable[Index].PhysicalBase;

diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf
@@ -52,15 +52,15 @@ FV = BL33_AP_UEFI
 
 # NV_VARIABLE_STORE
 0x007C0000|0x00010000
-gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
 
 # NV_FTW_WORKING header
 0x007D0000|0x00010000
-gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
 
 # NV_FTW_WORKING data
 0x007E0000|0x00010000
-gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
 
 ################################################################################
 #

diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc
@@ -260,10 +260,6 @@
   gRK3588TokenSpaceGuid.PcdAcpiUsb2StateDefault|$(ACPI_USB2_STATE_DISABLED)
 
 [PcdsDynamicDefault.common]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
-
   #
   # Display
   #

diff --git a/edk2-rockchip/Silicon/Rockchip/RockchipPkg.dec b/edk2-rockchip/Silicon/Rockchip/RockchipPkg.dec
@@ -27,7 +27,7 @@
   gRockchipPlatformConfigAppliedProtocolGuid = { 0xdf0e9b10, 0xcbd6, 0x496f, { 0x83, 0xd6, 0xef, 0xbb, 0x96, 0x9c, 0xe5, 0x3d } }
   gDpPhyProtocolGuid = { 0xb4bcf881, 0xc8b3, 0x46d7, { 0xaf, 0xbe, 0x5a, 0x2d, 0x94, 0x9d, 0x93, 0xc3 } }
   gPca95xxProtocolGuid = { 0x7e91391b, 0xa23c, 0x4a51, { 0x9d, 0xf7, 0xf6, 0x74, 0xef, 0x1d, 0x51, 0x1b } }
-  
+
 [Guids]
   gRockchipTokenSpaceGuid = { 0xc620b83a, 0x3175, 0x11ec, { 0x95, 0xb4, 0xf4, 0x2a, 0x7d, 0xcb, 0x92, 0x5d } }
   gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
@@ -79,9 +79,6 @@
   gRockchipTokenSpaceGuid.FspiBaseAddr|0|UINT64|0x21200003
   gRockchipTokenSpaceGuid.CruBaseAddr|0|UINT64|0x21200008
 
-  gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|0|UINT32|0x21200005
-  gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|0|UINT32|0x21200006
-  gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|0|UINT32|0x21200007
   gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash|FALSE|BOOLEAN|0x21200009
 
   gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0|UINT32|0x32000001
@@ -92,6 +89,6 @@
   gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase|0x0010f000|UINT64|0x00001000
   gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize|0x100|UINT32|0x00001001
   gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSmcId|0x82000010|UINT32|0x00010002
-  
+
   gRockchipTokenSpaceGuid.PcdPca9555Address|0|UINT8|0x03000001
   gRockchipTokenSpaceGuid.PcdPca9555Bus|0|UINT8|0x03000002