Add SARADC reading library

Signed-off-by: Mario Bălănică <[email protected]>
edk2-porting · Dec 18, 2024 · bbc91e0 · bbc91e0
1 parent 3bb6db9
commit bbc91e0
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Showing 7 changed files with 208 additions and 3 deletions.
diff --git a/edk2-rockchip/Silicon/Rockchip/Include/Library/CruLib.h b/edk2-rockchip/Silicon/Rockchip/Include/Library/CruLib.h
@@ -206,7 +206,7 @@ typedef enum {
         .gate = _gate,                                                   \
     }
 
-#define CRU_RESET_INIT(id, _regBase, _srstOffset, _srst)                 \
+#define CRU_RESET_INIT(_id, _regBase, _srstOffset, _srst)                 \
     [_id] = {                                                            \
         .regBase = _regBase,                                             \
         .srstOffset = _srstOffset,                                       \

diff --git a/edk2-rockchip/Silicon/Rockchip/Include/Library/SaradcLib.h b/edk2-rockchip/Silicon/Rockchip/Include/Library/SaradcLib.h
@@ -0,0 +1,18 @@
+/** @file
+ *
+ *  Copyright (c) 2024, Mario Bălănică <[email protected]>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef SARADC_LIB_H__
+#define SARADC_LIB_H__
+
+RETURN_STATUS
+SaradcReadChannel (
+  IN  UINT32  Channel,
+  OUT UINT32  *Data
+  );
+
+#endif /* SARADC_LIB_H__ */
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Soc.h b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Soc.h
@@ -73,11 +73,13 @@ typedef enum {
     CLK_I2S0_8CH_TX_SRC,
     MCLK_I2S0_8CH_TX,
     MCLK_I2S1_8CH_TX,
+    CLK_SARADC,
     CLK_COUNT
 } RK3588_CLOCK_IDS;
 
 typedef enum {
-  RESET_COUNT = 0
+    RESET_SRST_P_SARADC = 0,
+    RESET_COUNT
 } RK3588_RESET_IDS;
 
 #ifdef __cplusplus

diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon/RK3588CruLib.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon/RK3588CruLib.c
@@ -195,10 +195,15 @@ static CRU_CLOCK Clocks[CLK_COUNT] = {
     CRU_CLOCK_NODIV_INIT (MCLK_I2S1_8CH_TX, PMU1CRU_BASE,
         CRU_CLKSEL_CON_OFFSET, MCLK_I2S1_8CH_TX_SEL,
         CRU_CLKGATE_CON_OFFSET, MCLK_I2S1_8CH_TX_GATE),
+    CRU_CLOCK_INIT (CLK_SARADC, CRU_BASE,
+        CRU_CLKSEL_CON_OFFSET, CLK_SARADC_SEL,
+        CRU_CLKSEL_CON_OFFSET, CLK_SARADC_DIV,
+        CRU_CLKGATE_CON_OFFSET, CLK_SARADC_GATE),
 };
 
 static CRU_RESET Resets[RESET_COUNT] = {
-    // TO-DO
+    CRU_RESET_INIT (RESET_SRST_P_SARADC, CRU_BASE,
+        CRU_SOFTRST_CON_OFFSET, SRST_P_SARADC),
 };
 
 /********************* Private Variable Definition ***************************/
@@ -335,6 +340,14 @@ HAL_CRU_ClkGetFreq(uint32_t clockId)
         ASSERT (HAL_CRU_ClkGetMux(clockId) == 2);
         pRate = s_v0pllFreq;
         break;
+
+    case CLK_SARADC:
+        if (HAL_CRU_ClkGetMux(clockId) == 1) {
+            pRate = PLL_INPUT_OSC_RATE;
+        } else {
+            pRate = s_gpllFreq;
+        }
+        break;
     default:
         break;
     }
@@ -462,6 +475,16 @@ HAL_CRU_ClkSetFreq(uint32_t clockId, uint32_t rate)
             error = HAL_CRU_ClkSetFreq(PLL_V0PLL, div * rate);
         }
         return error;
+
+    case CLK_SARADC:
+         if (PLL_INPUT_OSC_RATE % rate == 0){
+            pRate = PLL_INPUT_OSC_RATE;
+            mux = 1;
+        } else {
+            pRate = s_gpllFreq;
+            mux = 0;
+        }
+        break;
     default:
         break;
     }

diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/SaradcLib/SaradcLib.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/SaradcLib/SaradcLib.c
@@ -0,0 +1,131 @@
+/** @file
+ *
+ *  Copyright (c) 2024, Mario Bălănică <[email protected]>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Library/BaseLib.h>
+#include <Library/CruLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/SaradcLib.h>
+#include <Library/TimerLib.h>
+
+#define SARADC_BASE  0xfec10000
+
+#define SARADC_CLOCK_RATE     1000000
+#define SARADC_CHANNEL_COUNT  8
+#define SARADC_RESOLUTION     12
+#define SARADC_DATA_MASK      (1 << SARADC_RESOLUTION) - 1
+
+#define SARADC_TIMEOUT_US  100000
+
+#define SARADC_CONV_CON         0x0000
+#define  SARADC_SINGLE_PD_MODE  BIT5
+#define  SARADC_START           BIT4
+#define SARADC_T_PD_SOC         0x0004
+#define SARADC_T_AS_SOC         0x0008
+#define SARADC_T_DAS_SOC        0x000C
+#define SARADC_T_SEL_SOC        0x0010
+#define SARADC_HIGH_COMP_BASE   0x0014
+#define SARADC_LOW_COMP_BASE    0x0054
+#define SARADC_DEBOUNCE         0x0094
+#define SARADC_HT_INT_EN        0x0098
+#define SARADC_LT_INT_EN        0x009C
+#define SARADC_MT_INT_EN        0x0100
+#define SARADC_END_INT_EN       0x0104
+#define SARADC_ST_CON           0x0108
+#define SARADC_STATUS           0x010C
+#define SARADC_END_INT_ST       0x0110
+#define SARADC_HT_INT_ST        0x0114
+#define SARADC_LT_INT_ST        0x0118
+#define SARADC_MT_INT_ST        0x011C
+#define SARADC_DATA_BASE        0x0120
+#define SARADC_AUTO_CH_EN       0x0160
+
+#define SARADC_END_INT  BIT0
+
+#define WRITE_ENABLE_SHIFT  16
+
+STATIC
+VOID
+SaradcReset (
+  VOID
+  )
+{
+  HAL_CRU_RstAssert (RESET_SRST_P_SARADC);
+  MicroSecondDelay (10);
+  HAL_CRU_RstDeassert (RESET_SRST_P_SARADC);
+}
+
+STATIC
+VOID
+SaradcStartChannel (
+  IN UINT32  Channel
+  )
+{
+  UINT32  Value;
+
+  // Changing channels without a reset leads to glitches...
+  SaradcReset ();
+
+  MmioWrite32 (SARADC_BASE + SARADC_T_PD_SOC, 0x20);
+  MmioWrite32 (SARADC_BASE + SARADC_T_DAS_SOC, 0xc);
+
+  Value = SARADC_END_INT;
+  MmioWrite32 (SARADC_BASE + SARADC_END_INT_EN, (Value << WRITE_ENABLE_SHIFT) | Value);
+
+  Value = SARADC_START | SARADC_SINGLE_PD_MODE | Channel;
+  MmioWrite32 (SARADC_BASE + SARADC_CONV_CON, (Value << WRITE_ENABLE_SHIFT) | Value);
+}
+
+RETURN_STATUS
+SaradcReadChannel (
+  IN  UINT32  Channel,
+  OUT UINT32  *Data
+  )
+{
+  UINTN   Retry;
+  UINT32  Value;
+
+  if ((Channel >= SARADC_CHANNEL_COUNT) || (Data == NULL)) {
+    ASSERT (FALSE);
+    return RETURN_INVALID_PARAMETER;
+  }
+
+  SaradcStartChannel (Channel);
+
+  for (Retry = SARADC_TIMEOUT_US; Retry > 0; Retry--) {
+    if (MmioRead32 (SARADC_BASE + SARADC_END_INT_ST) & SARADC_END_INT) {
+      break;
+    }
+
+    MicroSecondDelay (1);
+  }
+
+  if (Retry == 0) {
+    return RETURN_TIMEOUT;
+  }
+
+  MmioWrite32 (SARADC_BASE + SARADC_END_INT_ST, SARADC_END_INT);
+
+  *Data  = MmioRead32 (SARADC_BASE + SARADC_DATA_BASE + (Channel * sizeof (UINT32)));
+  *Data &= SARADC_DATA_MASK;
+
+  return RETURN_SUCCESS;
+}
+
+RETURN_STATUS
+EFIAPI
+SaradcLibConstructor (
+  VOID
+  )
+{
+  if (HAL_CRU_ClkGetFreq (CLK_SARADC) != SARADC_CLOCK_RATE) {
+    HAL_CRU_ClkSetFreq (CLK_SARADC, SARADC_CLOCK_RATE);
+  }
+
+  return RETURN_SUCCESS;
+}
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/SaradcLib/SaradcLib.inf b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/SaradcLib/SaradcLib.inf
@@ -0,0 +1,30 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <[email protected]>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SaradcLib
+  FILE_GUID                      = ff2f92c7-428e-49c0-8c39-91091ee278c0
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SaradcLib
+  CONSTRUCTOR                    = SaradcLibConstructor
+
+[Sources]
+  SaradcLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[LibraryClasses]
+  BaseLib
+  CruLib
+  DebugLib
+  IoLib
+  TimerLib
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc
@@ -136,6 +136,7 @@
   # Other SoC-specific libraries
   OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
   GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  SaradcLib|Silicon/Rockchip/RK3588/Library/SaradcLib/SaradcLib.inf
 
 [LibraryClasses.common.SEC]
   MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf