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wb_openram_wrapper
wb_openram_wrapper PublicTiny wrapper for OpenRAM memory block, connected to Wishbone bus
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caravel_wb_openram
caravel_wb_openram PublicForked from efabless/caravel_user_project
Caravel user project built around 1kB OpenRAM macro and simple HyperRAM driver to provide more memory to Caravel SoC.
Verilog 2
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hyperram_cyclonev_pcb
hyperram_cyclonev_pcb PublicSimple PCB to connect HyperRAM memories to Cyclone V SoC Development Kit via HSMC connector
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gf180-wb-hyperram
gf180-wb-hyperram PublicWishbone connected HyperRAM controller for GF180
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