Merge pull request #296 from ogamespec/main

clkgen cells map
emu-russia · Sep 16, 2024 · 4eb6c15 · 4eb6c15
2 parents 0a917e5 + 5de936d
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diff --git a/imgstore/modules/soc/dffr_tran.jpg b/imgstore/modules/soc/dffr_tran.jpg
diff --git a/imgstore/soc/clkgen.jpg b/imgstore/soc/clkgen.jpg
diff --git a/wiki/soc/cells.md b/wiki/soc/cells.md
@@ -67,8 +67,13 @@ The topology is not complete (m1 is missing in some places), but it is sufficien
 
 ## dffr - Posedge DFF With Single-rail CLK Synchronous Dual-rail Inverse Polarity Reset Q/NQ Output (DFFR_B2)
 
+The #res input is fed separately to the Master and Slave MUX so that synchronous reset can be done. But usually #res1 and #res2 are connected externally, so the DFF becomes with asynchronous reset.
+The dual-rail ck/cck signals are obtained locally by demultiplexing the CLK input signal.
+
 ![dffr](/imgstore/modules/soc/dffr.jpg)
 
+![dffr_tran](/imgstore/modules/soc/dffr_tran.jpg)
+
 ## dffr_comp (DFFR_A)
 
 ![dffr_comp](/imgstore/modules/soc/dffr_comp.jpg)

diff --git a/wiki/soc/clkgen.md b/wiki/soc/clkgen.md
@@ -33,3 +33,10 @@ The names of signals of the CLK group have many synonyms used by different autho
 |clk8|output|To Core| (Aka BOMA_1MHZ,MAIN_CLK_N)|
 |clk9|output|To Core,MMIO,APU| (Aka BOGA_1MHZ,MAIN_CLK_P)|
 |cclk|output|To APU,PPU| (Aka AZOF)|
+
+## Map
+
+|Row|Cells|
+|---|---|
+|1|not, not, not2(unused), not3, nand, nor, not2(unused), not3, nor, oan, not, not2, or, dffrnq_comp, nor_latch, nor, not, not, dffrnq_comp, not, dffrnq_comp, not, dffrnq_comp, not, dffrnq_comp, not, not2, nand, nand, not, not6 |
+|2|not6, not6, or, not, not, nand3, not, not2(unused), not2(unused), not2(unused), not2(unused), not2(unused), not, not, nand4, not6, not, not, nor3, not4+not6, not4+not6, not2, nor3, not4+not6, not4+not6, not2, nor, not6, not6, and, not, not |