liteeth_phy: Merge a7_2500basex in a7_1000basex and handle changes th…

…rough linerate.

liteeth/phy/__init__.py

@@ -34,7 +34,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
 from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as LiteEthECP5PHYRGMII
 
 from liteeth.phy.a7_1000basex      import A7_1000BASEX
-from liteeth.phy.a7_2500basex      import A7_2500BASEX
+from liteeth.phy.a7_1000basex      import A7_2500BASEX
 from liteeth.phy.k7_1000basex      import K7_1000BASEX
 from liteeth.phy.ku_1000basex      import KU_1000BASEX
 from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX

liteeth/phy/a7_1000basex.py

@@ -2,7 +2,8 @@
 # This file is part of MiSoC and has been adapted/modified for LiteEth.
 #
 # Copyright (c) 2018 Sebastien Bourdeauducq <[email protected]>
-# Copyright (c) 2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2020-2024 Florent Kermarrec <[email protected]>
+# Copyright (c) 2023 Sergey Razumov <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
@@ -21,8 +22,9 @@
 
 class A7_1000BASEX(LiteXModule):
     dw          = 8
-    tx_clk_freq = 125e6
+    linerate    = 1.25e9
     rx_clk_freq = 125e6
+    tx_clk_freq = 125e6
     def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_polarity=0, tx_polarity=0):
         pcs = PCS(lsb_first=True)
         self.submodules += pcs
@@ -200,7 +202,10 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_pola
             p_RX_DEFER_RESET_BUF_EN      = "TRUE",
 
             # CDR Attributes
-            p_RXCDR_CFG                  = 0x0001107FE086021101010,
+            p_RXCDR_CFG                  = {
+                1.25e9 : 0x0001107FE086021101010,
+                2.5e9  : 0x0000107FE206001041010,
+            }[self.linerate],
             p_RXCDR_FR_RESET_ON_EIDLE    = 0b0,
             p_RXCDR_HOLD_DURING_EIDLE    = 0b0,
             p_RXCDR_PH_RESET_ON_EIDLE    = 0b0,
@@ -318,10 +323,10 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_pola
             p_SATA_PLL_CFG               = "VCO_3000MHZ",
 
             # RX Fabric Clock Output Control Attributes
-            p_RXOUT_DIV                  = 4,
+            p_RXOUT_DIV                  = {1.25e9 : 4, 2.5e9 : 2}[self.linerate],
 
             # TX Fabric Clock Output Control Attributes
-            p_TXOUT_DIV                  = 4,
+            p_TXOUT_DIV                  = {1.25e9 : 4, 2.5e9 : 2}[self.linerate],
 
             # RX Phase Interpolator Attributes
             p_RXPI_CFG0                  = 0b000,
@@ -700,17 +705,17 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_pola
 
         # TX MMCM.
         self.tx_mmcm = tx_mmcm = S7MMCM()
-        tx_mmcm.register_clkin(txoutclk_rebuffer,   62.5e6)
-        tx_mmcm.create_clkout(self.cd_eth_tx_half,  62.5e6, buf="bufh", with_reset=False)
-        tx_mmcm.create_clkout(self.cd_eth_tx,      125.0e6, buf="bufh", with_reset=True)
+        tx_mmcm.register_clkin(txoutclk_rebuffer,  self.tx_clk_freq/2)
+        tx_mmcm.create_clkout(self.cd_eth_tx_half, self.tx_clk_freq/2, buf="bufh", with_reset=False)
+        tx_mmcm.create_clkout(self.cd_eth_tx,      self.tx_clk_freq,   buf="bufh", with_reset=True)
         self.comb += tx_mmcm.reset.eq(tx_mmcm_reset)
         self.comb += tx_mmcm_locked.eq(tx_mmcm.locked)
 
         # RX MMCM.
         self.rx_mmcm = rx_mmcm = S7MMCM()
-        rx_mmcm.register_clkin(rxoutclk_rebuffer,   62.5e6)
-        rx_mmcm.create_clkout(self.cd_eth_rx_half,  62.5e6, buf="bufg", with_reset=False)
-        rx_mmcm.create_clkout(self.cd_eth_rx,      125.0e6, buf="bufg", with_reset=True)
+        rx_mmcm.register_clkin(rxoutclk_rebuffer,  self.rx_clk_freq/2)
+        rx_mmcm.create_clkout(self.cd_eth_rx_half, self.rx_clk_freq/2, buf="bufg", with_reset=False)
+        rx_mmcm.create_clkout(self.cd_eth_rx,      self.rx_clk_freq,   buf="bufg", with_reset=True)
         self.comb += rx_mmcm.reset.eq(rx_mmcm_reset)
         self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
 
@@ -747,7 +752,7 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_pola
         ]
 
         # Assume CDR lock time is 50,000 UI as per DS183 and similar to what the Xilinx wizards does.
-        cdr_lock_time = round(sys_clk_freq*50e3/1.25e9)
+        cdr_lock_time = round(sys_clk_freq*50e3/self.linerate)
         cdr_lock_counter = Signal(max=cdr_lock_time+1)
         cdr_locked = Signal()
         self.sync += [
@@ -776,3 +781,10 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_pola
     def add_csr(self):
         self._reset = CSRStorage()
         self.comb += self.reset.eq(self._reset.storage)
+
+# A7_2500BASEX PHY ---------------------------------------------------------------------------------
+
+class A7_2500BASEX(A7_1000BASEX):
+    linerate    = 2.5e9
+    rx_clk_freq = 312.5e6
+    tx_clk_freq = 312.5e6