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phy/gw5rgmii: avoid synthesis noise by adding missing in/out ports fo…
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…r IODELAY primitives
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@trabucayre
trabucayre committed Jan 8, 2024
1 parent 1c9acfe commit 1ea28bd
Showing 1 changed file with 20 additions and 2 deletions.
22 changes: 20 additions & 2 deletions liteeth/phy/gw5rgmii.py
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,11 @@ def __init__(self, pads):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = 0,
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = tx_ctl_oddrx1f,
o_DF = Open(),
o_DO = pads.tx_ctl,
)
]
Expand All @@ -58,8 +62,12 @@ def __init__(self, pads):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = 0,
i_DI = tx_data_oddrx1f[i],
o_DO = pads.tx_data[i],
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = tx_data_oddrx1f[i],
o_DF = Open(),
o_DO = pads.tx_data[i],
)
]
self.comb += sink.ready.eq(1)
Expand All @@ -85,7 +93,11 @@ def __init__(self, pads, rx_delay=2e-9):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = rx_delay_taps,
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = pads.rx_ctl,
o_DF = Open(),
o_DO = rx_ctl_delayf,
),
DDRInput(
Expand All @@ -101,7 +113,11 @@ def __init__(self, pads, rx_delay=2e-9):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = rx_delay_taps,
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = pads.rx_data[i],
o_DF = Open(),
o_DO = rx_data_delayf[i]),
DDRInput(
clk = ClockSignal("eth_rx"),
Expand Down Expand Up @@ -160,6 +176,8 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9, tx_clk=N
i_DI = eth_tx_clk_o,
i_DLYSTEP = self._txdelay_taps.storage,
i_SDTAP = 1,
i_VALUE = 0, # FIXME
o_DF = Open(),
o_DO = clock_pads.tx,
)
]
Expand Down

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