Skip to content

Commit

Permalink
phy/Ultrascale/1000BaseX: Switch to LiteICLink's ChannelPLL for more …
Browse files Browse the repository at this point in the history 
…flexibility/simplicity.

LiteICLink's ChannelPLL directly computes the CPLL/DIV parameters.
  • Loading branch information
@enjoy-digital
enjoy-digital committed Feb 7, 2024
1 parent 8f521d8 commit 80ba793
Show file tree
Hide file tree
Showing 3 changed files with 39 additions and 21 deletions.
24 changes: 15 additions & 9 deletions liteeth/phy/ku_1000basex.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,19 +11,21 @@

from litex.gen import *

from liteiclink.serdes.gth3_ultrascale import GTHChannelPLL

from liteeth.common import *
from liteeth.phy.pcs_1000basex import *

# KU_1000BASEX PHY ---------------------------------------------------------------------------------

class KU_1000BASEX(LiteXModule):
# Configured for 200MHz transceiver reference clock
# Configured for 200MHz or 156.25MHz transceiver reference clock
dw = 8
linerate = 1.25e9
rx_clk_freq = 125e6
tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
assert refclk_freq in [200e6]
assert refclk_freq in [200e6, 156.25e6]
pcs = PCS(lsb_first=True)
self.submodules += pcs

Expand Down Expand Up @@ -69,6 +71,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
rx_data = Signal(20)
rx_reset_done = Signal()

pll = GTHChannelPLL(refclk, refclk_freq, self.linerate)
self.submodules.pll = pll
print(pll)

gth_params = dict(
p_ACJTAG_DEBUG_MODE = 0b0,
p_ACJTAG_MODE = 0b0,
Expand Down Expand Up @@ -123,12 +129,12 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_CPLL_CFG1 = 0b1010010010101100,
p_CPLL_CFG2 = 0b0000000000000111,
p_CPLL_CFG3 = 0b000000,
p_CPLL_FBDIV = 5,
p_CPLL_FBDIV_45 = 5,
p_CPLL_FBDIV = pll.config["n2"],
p_CPLL_FBDIV_45 = pll.config["n1"],
p_CPLL_INIT_CFG0 = 0b0000001010110010,
p_CPLL_INIT_CFG1 = 0b00000000,
p_CPLL_LOCK_CFG = 0b0000000111101000,
p_CPLL_REFCLK_DIV = 2,
p_CPLL_REFCLK_DIV = pll.config["m"],
p_DDI_CTRL = 0b00,
p_DDI_REALIGN_WAIT = 15,
p_DEC_MCOMMA_DETECT = "FALSE",
Expand Down Expand Up @@ -291,7 +297,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_RXOOB_CFG = 0b000000110,
p_RXOOB_CLK_CFG = "PMA",
p_RXOSCALRESET_TIME = 0b00011,
p_RXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_RXOUT_DIV = pll.config["d"],
p_RXPCSRESET_TIME = 0b00011,
p_RXPHBEACON_CFG = 0b0000000000000000,
p_RXPHDLY_CFG = 0b0010000000100000,
Expand Down Expand Up @@ -320,7 +326,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_RX_BIAS_CFG0 = 0b0000101010110100,
p_RX_BUFFER_CFG = 0b000000,
p_RX_CAPFF_SARC_ENB = 0b0,
p_RX_CLK25_DIV = 8,
p_RX_CLK25_DIV = {200e6: 8, 156.25e6: 7}[refclk_freq],
p_RX_CLKMUX_EN = 0b1,
p_RX_CLK_SLIP_OVRD = 0b00000,
p_RX_CM_BUF_CFG = 0b1010,
Expand Down Expand Up @@ -396,7 +402,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_TXFIFO_ADDR_CFG = "LOW",
p_TXGBOX_FIFO_INIT_RD_ADDR = 4,
p_TXGEARBOX_EN = "FALSE",
p_TXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_TXOUT_DIV = pll.config["d"],
p_TXPCSRESET_TIME = 0b00011,
p_TXPHDLY_CFG0 = 0b0010000000100000,
p_TXPHDLY_CFG1 = 0b0000000001110101,
Expand All @@ -419,7 +425,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_TXSYNC_MULTILANE = 0b0,
p_TXSYNC_OVRD = 0b0,
p_TXSYNC_SKIP_DA = 0b0,
p_TX_CLK25_DIV = 8,
p_TX_CLK25_DIV = {200e6: 8, 156.25e6: 7}[refclk_freq],
p_TX_CLKMUX_EN = 0b1,
p_TX_DATA_WIDTH = 20,
p_TX_DCD_CFG = 0b000010,
Expand Down
18 changes: 12 additions & 6 deletions liteeth/phy/usp_gth_1000basex.py
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#
# This file is part of LiteEth.
#
# Copyright (c) 2019-2023 Florent Kermarrec <[email protected]>
# Copyright (c) 2019-2024 Florent Kermarrec <[email protected]>
# Copyright (c) 2018 Sebastien Bourdeauducq <[email protected]>
# SPDX-License-Identifier: BSD-2-Clause

Expand All @@ -11,6 +11,8 @@

from litex.gen import *

from liteiclink.serdes.gth4_ultrascale import GTHChannelPLL

from liteeth.common import *
from liteeth.phy.pcs_1000basex import *

Expand Down Expand Up @@ -69,6 +71,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
rx_data = Signal(20)
rx_reset_done = Signal()

pll = GTHChannelPLL(refclk, refclk_freq, self.linerate)
self.submodules.pll = pll
print(pll)

gth_params = dict(
p_ACJTAG_DEBUG_MODE = 0b0,
p_ACJTAG_MODE = 0b0,
Expand Down Expand Up @@ -136,11 +142,11 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_CPLL_CFG1 = 0b0000000000100011,
p_CPLL_CFG2 = 0b0000000000000010,
p_CPLL_CFG3 = 0b000000,
p_CPLL_FBDIV = {200e6: 5, 156.25e6: 4}[refclk_freq],
p_CPLL_FBDIV_45 = {200e6: 5, 156.25e6: 4}[refclk_freq],
p_CPLL_FBDIV = pll.config["n2"],
p_CPLL_FBDIV_45 = pll.config["n1"],
p_CPLL_INIT_CFG0 = 0b0000001010110010,
p_CPLL_LOCK_CFG = 0b0000000111101000,
p_CPLL_REFCLK_DIV = {200e6: 2, 156.25e6: 1}[refclk_freq],
p_CPLL_REFCLK_DIV = pll.config["m"],
p_CTLE3_OCAP_EXT_CTRL = 0b000,
p_CTLE3_OCAP_EXT_EN = 0b0,
p_DDI_REALIGN_WAIT = 15,
Expand Down Expand Up @@ -332,7 +338,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_RXOOB_CFG = 0b000000110,
p_RXOOB_CLK_CFG = "PMA",
p_RXOSCALRESET_TIME = 0b00011,
p_RXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_RXOUT_DIV = pll.config["d"],
p_RXPCSRESET_TIME = 0b00011,
p_RXPHBEACON_CFG = 0b0000000000000000,
p_RXPHDLY_CFG = 0b0010000001110000,
Expand Down Expand Up @@ -443,7 +449,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_TXFIFO_ADDR_CFG = "LOW",
p_TXGBOX_FIFO_INIT_RD_ADDR = 4,
p_TXGEARBOX_EN = "FALSE",
p_TXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_TXOUT_DIV = pll.config["d"],
p_TXPCSRESET_TIME = 0b00011,
p_TXPHDLY_CFG0 = 0b0110000001110000,
p_TXPHDLY_CFG1 = 0b0000000000001111,
Expand Down
18 changes: 12 additions & 6 deletions liteeth/phy/usp_gty_1000basex.py
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#
# This file is part of LiteEth.
#
# Copyright (c) 2019-2023 Florent Kermarrec <[email protected]>
# Copyright (c) 2019-2024 Florent Kermarrec <[email protected]>
# Copyright (c) 2018 Sebastien Bourdeauducq <[email protected]>
# SPDX-License-Identifier: BSD-2-Clause

Expand All @@ -11,6 +11,8 @@

from litex.gen import *

from liteiclink.serdes.gty_ultrascale import GTYChannelPLL

from liteeth.common import *
from liteeth.phy.pcs_1000basex import *

Expand Down Expand Up @@ -69,6 +71,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
rx_data = Signal(20)
rx_reset_done = Signal()

pll = GTYChannelPLL(refclk, refclk_freq, self.linerate)
self.submodules.pll = pll
print(pll)

gty_params = dict(
p_ACJTAG_DEBUG_MODE = 0b0,
p_ACJTAG_MODE = 0b0,
Expand Down Expand Up @@ -137,11 +143,11 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_CPLL_CFG1 = 0b0000000000101011,
p_CPLL_CFG2 = 0b0000000000000010,
p_CPLL_CFG3 = 0b0000000000000000,
p_CPLL_FBDIV = {200e6: 5, 156.25e6: 4}[refclk_freq],
p_CPLL_FBDIV_45 = {200e6: 5, 156.25e6: 4}[refclk_freq],
p_CPLL_FBDIV = pll.config["n2"],
p_CPLL_FBDIV_45 = pll.config["n1"],
p_CPLL_INIT_CFG0 = 0b0000001010110010,
p_CPLL_LOCK_CFG = 0b0000000111101000,
p_CPLL_REFCLK_DIV = {200e6: 2, 156.25e6: 1}[refclk_freq],
p_CPLL_REFCLK_DIV = pll.config["m"],
p_CTLE3_OCAP_EXT_CTRL = 0b000,
p_CTLE3_OCAP_EXT_EN = 0b0,
p_DDI_CTRL = 0b00,
Expand Down Expand Up @@ -355,7 +361,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_RXOOB_CFG = 0b000000110,
p_RXOOB_CLK_CFG = "PMA",
p_RXOSCALRESET_TIME = 0b00011,
p_RXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_RXOUT_DIV = pll.config["d"],
p_RXPCSRESET_TIME = 0b00011,
p_RXPHBEACON_CFG = 0b0000000000000000,
p_RXPHDLY_CFG = 0b0010000001110000,
Expand Down Expand Up @@ -467,7 +473,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e
p_TXFIFO_ADDR_CFG = "LOW",
p_TXGBOX_FIFO_INIT_RD_ADDR = 4,
p_TXGEARBOX_EN = "FALSE",
p_TXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_TXOUT_DIV = pll.config["d"],
p_TXPCSRESET_TIME = 0b00011,
p_TXPHDLY_CFG0 = 0b0110000001110000,
p_TXPHDLY_CFG1 = 0b0000000000001111,
Expand Down

0 comments on commit 80ba793

Please sign in to comment.