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CGRA configurable size and instruction update (#21)
* Reconfigurable for CGRA size * Adding, renaming, removing many file to make the cgra peripheral registers configurable and the software driver compatible. * Removing unwanted files being tracked. * Folder renaming. * FFT example updated and CGRA rtl debugged. * python script for bitsream generation updated with template. * CGRA app code cleaning. * Added manual control over incrementation for LWD and SWD instructions on the CGRA. * CGRA vendor update. * CGRA vendor update for regtool.py execution. * Weird error solved by changing the printf. * Save commit * Save commit * Save commit. * Simple check app working with any CGRA size. * Example CGRA check size cleaned. * Updating lint rules to be compatible with any CGRA size. * Added error check on cgra_size app. * File renaming and CGRA driver updated for any CGRA size. * Added X extension parameter to testharness and top module. * Renaming all cgra_x_heep reference to heepsilon. * Removed dummy header file not needed anymore with new xheep flow. * run verible. * Few remaining old name changed. * testharness and top modules updated. * Put default 4x4 CGRA size. * Code cleaning. * Modified CGRA toe be compatible with single row or column. * Added CGRA size to debug printf. * Removing changes to x-heep vendor repo. * Updated tb_util for new memory bank organization. * CGRA vendor version updated. --------- Co-authored-by: Benoît Denkinger <benoit.denkinger@epfl.ch>
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// Copyright 2020 ETH Zurich and University of Bologna. | ||
// Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
// SPDX-License-Identifier: SHL-0.51 | ||
// Derived from Occamy: https://github.com/pulp-platform/snitch/blob/master/hw/system/occamy/src/occamy_cfg.hjson | ||
// Peripherals configuration for core-v-mini-mcu. | ||
{ | ||
cgra: { | ||
// Main impact: more columns equals more master ports connected to the bus | ||
// There is a maximum limit because of the kernel configuration size fixed to the bus width of 32 bits | ||
// This limit can be increased but manual changes are required | ||
// Maximum number of columns: 32-log2(rcs_num_instr)-log2(max_columns*rcs_num_instr) | ||
// Default settings enable: 32-log2(32)-log2(4*32) = 20 columns | ||
num_columns: 4 | ||
// Main impact: more rows equals to more context memory banks (i.e., one per row) | ||
// There should be no limitation compared to the number of rows compared to columns | ||
num_rows: 4 | ||
// It is possible to limit the maximum number of columns a kernel can use (this saves a bit of resources) | ||
// The default value should be the same than num_columns, put an number to change it | ||
max_columns: default | ||
// Number of instructions each RC can contain (usually a power of 2) | ||
rcs_num_instr: 32 | ||
// Context memory bank depth | ||
// This parameter is by default set to max_columns*rcs_num_instr | ||
// The default depth correspond to a minimum required in case a kernel uses max_columns and rcs_num_instr instructions per RC | ||
// The depth can be increased in case more kernels need to be stored inside the context memory | ||
cmem_bk_depth: default | ||
// This value fixes the maximum number of kernel configuration words that can be stores | ||
// It does not mean that the context memory can holds that many kernels, it depends on the size of each kernel | ||
// You probably don't need to change this value | ||
kmem_depth: 16 | ||
}, | ||
} |
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