-
Notifications
You must be signed in to change notification settings - Fork 83
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge branch 'esl-epfl:main' into main
- Loading branch information
Showing
52 changed files
with
2,225 additions
and
502 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| { | ||
| bus_type: "onetoM", | ||
| ram_banks: { | ||
| code_and_data: { | ||
| num: 6 | ||
| sizes: 32 | ||
| } | ||
| } | ||
|
|
||
| linker_sections: | ||
| [ | ||
| { | ||
| name: code | ||
| start: 0 | ||
| #minimum size for freeRTOS and clang | ||
| size: 0x00000C800 | ||
| }, | ||
| { | ||
| name: data | ||
| start: 0x00000C800 | ||
| } | ||
| ] | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,18 @@ | ||
| from x_heep_gen.linker_section import LinkerSection | ||
| from x_heep_gen.system import XHeep, BusType | ||
|
|
||
| def config(): | ||
| system = XHeep(BusType.NtoM) | ||
| system.add_ram_banks([32] * 2) | ||
| system.add_ram_banks_il(2, 64, "data_interleaved") | ||
|
|
||
| system.add_linker_section(LinkerSection.by_size("code", 0, 0x00000C800)) | ||
| system.add_linker_section(LinkerSection("data", 0x00000C800, None)) | ||
|
|
||
| # Here the system is build, | ||
| # The missing gaps are filled, like the missing end address of the data section. | ||
| system.build() | ||
| if not system.validate(): | ||
| raise RuntimeError("there are errors") | ||
|
|
||
| return system |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| { | ||
| bus_type: "NtoM", | ||
| ram_banks: { | ||
| code_and_data: { | ||
| sizes: 64 | ||
| } | ||
| more_data: { | ||
| type: continuous | ||
| num: 2 | ||
| sizes: 32 | ||
| } | ||
| data_interleaved: { | ||
| auto_section: auto | ||
| // the name is used by example_matadd_interleaved as .xheep_data_interleaved | ||
| type: interleaved | ||
| num: 4 | ||
| size: 16 | ||
| } | ||
| data_interleaved_2: { | ||
| auto_section: auto | ||
| type: interleaved | ||
| num: 2 | ||
| size: 16 | ||
| } | ||
| } | ||
|
|
||
| linker_sections: | ||
| [ | ||
| { | ||
| name: code | ||
| start: 0 | ||
| // minimum size for freeRTOS and clang | ||
| size: 0x00000C800 | ||
| }, | ||
| { | ||
| name: data | ||
| start: 0x00000C800 | ||
| } | ||
| ] | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| { | ||
| ram_address: 0 | ||
| bus_type: "onetoM", | ||
| ram_banks: { | ||
| code_and_data: { | ||
| num: 2 | ||
| sizes: [32] | ||
| } | ||
| } | ||
|
|
||
| linker_sections: | ||
| [ | ||
| { | ||
| name: code | ||
| start: 0 | ||
| #minimum size for freeRTOS and clang | ||
| size: 0x00000C800 | ||
| }, | ||
| { | ||
| name: data | ||
| start: 0x00000C800 | ||
| } | ||
| ] | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| { | ||
| bus_type: "onetoM", | ||
| ram_banks: { | ||
| code_and_data: { | ||
| num: 3 | ||
| sizes: 32 | ||
| } | ||
| } | ||
|
|
||
| linker_sections: | ||
| [ | ||
| { | ||
| name: code | ||
| start: 0 | ||
| #minimum size for freeRTOS and clang | ||
| size: 0x00000C800 | ||
| }, | ||
| { | ||
| name: data | ||
| start: 0x00000C800 | ||
| } | ||
| ] | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,72 @@ | ||
| CAPI=2: | ||
|
|
||
| # Copyright 2024 EPFL | ||
| # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. | ||
| # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 | ||
|
|
||
| name: openhwgroup.org:systems:core-v-mini-mcu-fpga | ||
| description: CORE-V MINI-MCU FPGA related files. | ||
|
|
||
| filesets: | ||
| rtl-fpga: | ||
| depend: | ||
| - x-heep::packages | ||
| files: | ||
| - hw/fpga/sram_wrapper.sv | ||
| file_type: systemVerilogSource | ||
|
|
||
| ip-fpga: | ||
| files: | ||
| - hw/fpga/scripts/generate_sram.tcl: { file_type: tclSource } | ||
| - hw/fpga/prim_xilinx_clk.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/cv32e40p_xilinx_clock_gate.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/cv32e40x_xilinx_clock_gate.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/cve2_xilinx_clock_gate.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/cv32e40px_xilinx_clock_gate.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/pad_cell_input_xilinx.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/pad_cell_output_xilinx.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/pad_cell_inout_xilinx.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/pad_cell_bypass_input_xilinx.sv: { file_type: systemVerilogSource } | ||
| - hw/fpga/pad_cell_bypass_output_xilinx.sv: { file_type: systemVerilogSource } | ||
|
|
||
| ip-fpga-pynq-z2: | ||
| files: | ||
| - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } | ||
|
|
||
| ip-fpga-nexys: | ||
| files: | ||
| - hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } | ||
|
|
||
| ip-fpga-zcu104: | ||
| files: | ||
| - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } | ||
|
|
||
| xdc-fpga-nexys: | ||
| files: | ||
| - hw/fpga/constraints/nexys/pin_assign.xdc | ||
| - hw/fpga/constraints/nexys/constraints.xdc | ||
| file_type: xdc | ||
|
|
||
| xdc-fpga-pynq-z2: | ||
| files: | ||
| - hw/fpga/constraints/pynq-z2/pin_assign.xdc | ||
| - hw/fpga/constraints/pynq-z2/constraints.xdc | ||
| file_type: xdc | ||
|
|
||
| xdc-fpga-zcu104: | ||
| files: | ||
| - hw/fpga/constraints/zcu104/pin_assign.xdc | ||
| file_type: xdc | ||
|
|
||
|
|
||
| targets: | ||
| default: &default_target | ||
| filesets: | ||
| - rtl-fpga | ||
| - ip-fpga | ||
| - target_pynq-z2 ? (ip-fpga-pynq-z2) | ||
| - target_pynq-z2 ? (xdc-fpga-pynq-z2) | ||
| - target_nexys-a7-100t ? (ip-fpga-nexys) | ||
| - target_nexys-a7-100t ? (xdc-fpga-nexys) | ||
| - target_zcu104 ? (ip-fpga-zcu104) | ||
| - target_zcu104 ? (xdc-fpga-zcu104) |
Oops, something went wrong.