Merge branch 'main' into main

Makefile

@@ -134,7 +134,7 @@ verible:
 
 ## Generates the build folder in sw using CMake to build (compile and linking)
 ## @param PROJECT=<folder_name_of_the_project_to_be_built>
-## @param TARGET=sim(default),pynq-z2,nexys-a7-100t,zcu104
+## @param TARGET=sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104
 ## @param LINKER=on_chip(default),flash_load,flash_exec
 ## @param COMPILER=gcc(default), clang
 ## @param COMPILER_PREFIX=riscv32-unknown-(default)
@@ -153,10 +153,14 @@ app-compile-all:
 
 ## @section Simulation
 
-## Verilator simulation
+## Verilator simulation with C++
 verilator-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
+## Verilator simulation with SystemC
+verilator-sim-sc:
+	$(FUSESOC) --cores-root . run --no-export --target=sim_sc --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
+
 ## Questasim simulation
 questasim-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

README.md

@@ -231,11 +231,11 @@ make app
 To run any other application, please use the following command with appropiate parameters:
 
 ```
-app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),pynq-z2,nexys-a7-100t,zcu104 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
+app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
 
 Params:
 - PROJECT (ex: <folder_name_of_the_project_to_be_built>, hello_world(default))
-- TARGET (ex: sim(default),pynq-z2,nexys-a7-100t,zcu104)
+- TARGET (ex: sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104)
 - LINKER (ex: on_chip(default),flash_load,flash_exec)
 - COMPILER (ex: gcc(default),clang)
 - COMPILER_PREFIX (ex: riscv32-unknown-(default))
@@ -281,7 +281,7 @@ For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv
 you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
 Below the different EDA examples commands.
 
-### Compiling for Verilator
+### Compiling for Verilator (C++ testbench)
 
 To simulate your application with Verilator, first compile the HDL:
 
@@ -307,6 +307,39 @@ or to execute all these three steps type:
 make run-helloworld
 ```
 
+### Compiling for Verilator (SystemC testbench)
+
+To simulate your application with Verilator using `SystemC`,
+
+make sure you have `SystemC 2.3.3` installed, if not, find it [here](https://www.accellera.org/downloads/standards/systemc).
+
+Make sure to have the following env variables set:
+
+```
+export SYSTEMC_INCLUDE=/your_path_to_systemc/systemc/include/
+export SYSTEMC_LIBDIR=/your_path_to_systemc/systemc/lib-linux64/
+```
+
+Compile the HDL:
+
+```
+make verilator-sim-sc
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim_sc-verilator
+```
+
+and type to run your compiled software:
+
+```
+./Vtestharness +firmware=../../../sw/build/main.hex
+```
+
+If you want to know what is special about the SystemC testbench, have a look [here](./docs/source/How_to/SystemC.md)
+
 ### Compiling for VCS
 
 To simulate your application with VCS, first compile the HDL:

core-v-mini-mcu.core

@@ -203,6 +203,8 @@ filesets:
 
   tb-verilator:
     files:
+    - tb/XHEEP_CmdLineOptions.hh: { is_include_file: true }
+    - tb/XHEEP_CmdLineOptions.cpp
     - tb/tb_top.cpp
     file_type: cppSource
 
@@ -211,6 +213,14 @@ filesets:
     - tb/tb_top.sv
     file_type: systemVerilogSource
 
+  tb-sc-verilator:
+    files:
+    - tb/XHEEP_CmdLineOptions.hh: { is_include_file: true }
+    - tb/XHEEP_CmdLineOptions.cpp
+    - tb/tb_sc_top.cpp
+    file_type: cppSource
+
+
   openroad_base_files:
     files:
       - flow/OpenROAD-flow-scripts/flow/Makefile : {file_type: Makefile}
@@ -271,6 +281,10 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  SIM_SYSTEMC:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
   FPGA_NEXYS:
     datatype: bool
     paramtype: vlogdefine
@@ -315,6 +329,8 @@ targets:
     - files_rtl_generic
     - target_sim ? (rtl-simulation)
     - target_sim ? (tool_verilator? (files_verilator_waiver))
+    - target_sim_sc ? (rtl-simulation)
+    - target_sim_sc ? (tool_verilator? (files_verilator_waiver))
     toplevel: [core_v_mini_mcu]
 
   sim:
@@ -406,6 +422,40 @@ targets:
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - "-Wall"
 
+  sim_sc:
+    <<: *default_target
+    default_tool: modelsim
+    filesets_append:
+    - tb-utils
+    - tool_verilator? (tb-sc-verilator)
+    - "!integrated_heep? (x_heep_system)"
+    toplevel:
+    - tool_verilator? (testharness)
+    parameters:
+    - COREV_PULP
+    - FPU
+    - JTAG_DPI
+    - X_EXT
+    - USE_EXTERNAL_DEVICE_EXAMPLE
+    - USE_UPF
+    - REMOVE_OBI_FIFO
+    - SIM_SYSTEMC=true
+    tools:
+      verilator:
+        mode: sc
+        verilator_options:
+          - '--sc'
+          - '--trace'
+          - '--trace-structs'
+          - '--trace-params'
+          - '--trace-max-array 1024'
+          - '--x-assign unique'
+          - '--x-initial unique'
+          - '--exe tb_sc_top.cpp'
+          - '-CFLAGS "-std=c++11 -Wall -g -fpermissive"'
+          - '-LDFLAGS "-pthread -lutil -lelf $(SYSTEMC_LIBDIR)/libsystemc.a"'
+          - "-Wall"
+
   nexys-a7-100t:
     <<: *default_target
     default_tool: vivado

docs/source/How_to/Debug.md

@@ -40,7 +40,7 @@ Now we are going to Simulate debugging with core-v-mini-mcu.
 In this setup, OpenOCD communicates with the remote bitbang server by means of DPIs.
 The remote bitbang server is simplemented in the folder ./hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang and it will be compiled using fusesoc.
 
-### Verilator
+### Verilator (C++ only)
 
 To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the `JTAG DPI` functions:
 

docs/source/How_to/SystemC.md

@@ -0,0 +1,16 @@
+#  SystemC model
+
+Supporting SystemC model in `X-HEEP` is still a work-in-progress.
+However, a simple example is provided in the SystemC testbench available in `tb/tb_sc_top.cpp`.
+
+When compiling the `X-HEEP` with Verilator using SystemC, the above testbench is used for simulation.
+The testbench gets an `X-HEEP` external-memory `obi` master port to communicate with a SystemC memory model.
+
+Such model is very simple as meant to be an example and is provided in `tb/systemc_tb`.
+For those who want to extend the functionality of `X-HEEP` with SystemC, such examples can be used as starting point.
+
+The SystemC modules leverages `TLM-2.0` as well as baseline SystemC functionalities.
+
+The `X-HEEP` `obi` port is connected to a `C++` direct-mapped cache who handles `hit` and `miss` with pre-defined latencies.
+It uses `TLM-2.0` to communicate with the external SystemC memory on `miss` cache-transactions.
+A module in SystemC then communicates with the RTL SystemC model compiled by Verilator to provides read/write data.

hw/ip_examples/slow_memory/rtl/slow_memory.sv

@@ -79,26 +79,35 @@ module slow_memory #(
 
 
   always_comb begin
-    gnt_o = 1'b0;
-    rvalid_o = rvalid_q;
-    state_n = state_q;
-    counter_n = counter_q - 1;
-    rvalid_n = rvalid_q;
-
+    gnt_o       = 1'b0;
+    rvalid_o    = rvalid_q;
+    state_n     = state_q;
+    counter_n   = counter_q - 1;
+    rvalid_n    = rvalid_q;
+    mem_req     = '0;
+    mem_we      = '0;
+    mem_addr    = '0;
+    mem_wdata   = '0;
+    mem_be      = '0;
+    mem_req_n   = mem_req_q;
+    mem_we_n    = mem_we_q;
+    mem_addr_n  = mem_addr_q;
+    mem_wdata_n = mem_wdata_q;
+    mem_be_n    = mem_be_q;
     unique case (state_q)
 
       READY: begin
         rvalid_n = 1'b0;
         if (req_i) begin
           gnt_o = random1[0];
           if (gnt_o) begin
-            state_n   = WAIT_RVALID;
-            counter_n = random2[4:0] + 1;
-            mem_req_n <= req_i;
-            mem_we_n <= we_i;
-            mem_addr_n <= addr_i;
-            mem_wdata_n <= wdata_i;
-            mem_be_n <= be_i;
+            state_n     = WAIT_RVALID;
+            counter_n   = random2[4:0] + 1;
+            mem_req_n   = req_i;
+            mem_we_n    = we_i;
+            mem_addr_n  = addr_i;
+            mem_wdata_n = wdata_i;
+            mem_be_n    = be_i;
           end
         end
       end

hw/vendor/esl_epfl_cv32e40px.core

@@ -60,3 +60,4 @@ targets:
     - files_rtl
     - ff_regfile
     - target_sim? (files_clk_gate)
+    - target_sim_sc? (files_clk_gate)

hw/vendor/openhwgroup_cv32e20/cve2_top.core

@@ -75,6 +75,7 @@ targets:
       - tool_veriblelint ? (files_lint_verible)
       - files_rtl
       - target_sim ? (files_clk_gate)
+      - target_sim_sc ? (files_clk_gate)
     toplevel: cve2_top
     parameters:
       - tool_vivado ? (FPGA_XILINX=true)

hw/vendor/openhwgroup_cv32e40p.core

@@ -64,3 +64,4 @@ targets:
     - files_rtl
     - ff_regfile
     - target_sim? (files_clk_gate)
+    - target_sim_sc? (files_clk_gate)

hw/vendor/openhwgroup_cv32e40x.core

@@ -67,3 +67,4 @@ targets:
     filesets:
       - files_rtl
       - target_sim? (files_clk_gate)
+      - target_sim_sc? (files_clk_gate)

hw/vendor/patches/openhwgroup_cv32e20/cv32e20_core.patch

@@ -0,0 +1,12 @@
+diff --git a/cve2_top.core b/cve2_top.core
+index cb4e23b4..0d9d2c5c 100644
+--- a/cve2_top.core
++++ b/cve2_top.core
+@@ -75,6 +75,7 @@ targets:
+       - tool_veriblelint ? (files_lint_verible)
+       - files_rtl
+       - target_sim ? (files_clk_gate)
++      - target_sim_sc ? (files_clk_gate)
+     toplevel: cve2_top
+     parameters:
+       - tool_vivado ? (FPGA_XILINX=true)

hw/vendor/pulp_platform_gpio.core

@@ -39,6 +39,7 @@ targets:
     - rtl
     - "gpio-test? (testbench)"
     - target_sim? (clock-gate)
+    - target_sim_sc? (clock-gate)
     - target_asic_synthesis? (clock-gate)
     - target_asic_yosys_synthesis? (clock-gate)
     - target_nexys-a7-100t? (no-clock-gate)

hw/vendor/pulp_platform_tech_cells_generic.core

@@ -20,3 +20,4 @@ targets:
   default:
     filesets:
     - target_sim? (rtl_sim)
+    - target_sim_sc? (rtl_sim)

sw/CMakeLists.txt

@@ -63,19 +63,19 @@ FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS ${SOURCE_PATH}*.h)
 SET(dir_list_str "")
 FOREACH(file_path ${new_list})
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-  if(${file_path} MATCHES "/device/")
-    if(${file_path} MATCHES "/target/") # Add it if its not in target, or if its in target/${TARGET}
-      if(${file_path} MATCHES ${TARGET})
+  if(${file_path} MATCHES "${ROOT_PROJECT}device/")
+    if(${file_path} MATCHES "${ROOT_PROJECT}device/target/") # Add it if its not in target, or if its in target/${TARGET}
+      if(${file_path} MATCHES "${ROOT_PROJECT}device/target/${TARGET}")
         SET(add 1)
       endif()
     else()
       SET(add 1)
     endif()
   elseif(${file_path} MATCHES ${PROJECT})
     SET(add 1)
-  elseif( ( ${file_path} MATCHES "/freertos/" ) AND ( ${PROJECT} MATCHES "freertos" ) )
+  elseif( ( ${file_path} MATCHES "${ROOT_PROJECT}freertos/" ) AND ( ${PROJECT} MATCHES "freertos" ) )
     SET(add 1)
-  elseif( ${file_path} MATCHES "/external/" )
+  elseif( ${file_path} MATCHES "${ROOT_PROJECT}external/" )
     SET(add 1)
   endif()
 
@@ -124,9 +124,9 @@ SET( c_dir_list "" )
 SET( app_found 0 )
 FOREACH(file_path IN LISTS new_list)
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-  if(${file_path} MATCHES "/device/")
+  if(${file_path} MATCHES "${ROOT_PROJECT}device/")
     SET(add 1)
-  elseif( ${file_path} MATCHES "/external/" )
+  elseif( ${file_path} MATCHES "${ROOT_PROJECT}external/" )
     SET(add 1)
   elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES ${MAINFILE} ) )
     SET(add 1)
@@ -153,7 +153,7 @@ if( app_found EQUAL 0 )
   SET(c_dir_list "")
   FOREACH(file_path IN LISTS new_list)
     SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-    if(${file_path} MATCHES "/device/")
+    if(${file_path} MATCHES "${ROOT_PROJECT}device/")
       SET(add 1)
     elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES ${MAINFILE} ) )
       SET(add 1)

sw/applications/example_dma/main.c

@@ -208,7 +208,7 @@ int main(int argc, char *argv[])
 
 #endif // TEST_ADDRESS_MODE
 
-#ifndef TARGET_PYNQ_Z2
+#if defined(TARGET_SIM) || defined(TARGET_SYSTEMC)
 
 #ifdef TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
@@ -275,7 +275,7 @@ int main(int argc, char *argv[])
 #endif //TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
 #else
-    #pragma message( "TEST_ADDRESS_MODE_EXTERNAL_DEVICE is not executed on PYNQ Z2" )
+    #pragma message( "TEST_ADDRESS_MODE_EXTERNAL_DEVICE is not executed on target different than TARGET_SIM" )
 #endif
 
 #ifdef TEST_PENDING_TRANSACTION