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reduce FPGA frequencz to 15MHz to accomodate FPU #404

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merged 6 commits into from
Oct 17, 2023
Merged

reduce FPGA frequencz to 15MHz to accomodate FPU #404

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38e212b
update cv32e40p verilator waiver
davideschiavone Oct 16, 2023
a1a938b
update cv32e40px verilator waiver
davideschiavone Oct 16, 2023
1a01423
reduce FPGA frequency to 15MHz to accomodate FPU
davideschiavone Oct 16, 2023
2d5d84d
reduced baudrate uart fpga
davideschiavone Oct 17, 2023
3944895
update README
davideschiavone Oct 17, 2023
903b80a
Merge remote-tracking branch 'origin' into fpga_15MHz
davideschiavone Oct 17, 2023
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13 changes: 12 additions & 1 deletion README.md
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Expand Up @@ -514,9 +514,20 @@ to load the binaries with the HS2 cable over JTAG,
or follow the [ExecuteFromFlash](./ExecuteFromFlash.md)
guide if you have a FLASH attached to the FPGA.


Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running.

For example, if you want to run your application using flash_exec, do as follow:

compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec`

and then follow the [ExecuteFromFlash](./ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.

To look at the output of your printf, run in another terminal:

`picocom -b 9600 -r -l --imap lfcrlf /dev/ttyUSB2`

Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example).


### Linux-FEMU (Linux Fpga EMUlation)

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2 changes: 2 additions & 0 deletions docs/source/How_to/ExecuteFromFlash.md
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Expand Up @@ -19,6 +19,8 @@ These three modes are mainly controlled by the two inputs pins
| 1 | 1 | SPI Flash Execution |
| 1 | 0 | SPI Flash Loading |


On the FPGA, such inputs are mapped to two switch buttons.
Below, a description of the three modes is provided.

### JTAG Boot Procedure
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4 changes: 2 additions & 2 deletions hw/fpga/scripts/xilinx_generate_clk_wizard.tcl
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Expand Up @@ -5,7 +5,7 @@

set design_name xilinx_clk_wizard
set in_clk_freq_MHz 125
set out_clk_freq_MHz 20
set out_clk_freq_MHz 15

# Select board
set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
Expand All @@ -25,7 +25,7 @@ set_property -dict [ list \
CONFIG.CLKIN1_JITTER_PS {80.0} \
CONFIG.CLKOUT1_JITTER {172.798} \
CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \
CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {50.000} \
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4 changes: 2 additions & 2 deletions sw/device/target/pynq-z2/x-heep.h
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Expand Up @@ -12,8 +12,8 @@ extern "C" {
#endif // __cplusplus


#define REFERENCE_CLOCK_Hz 20*1000*1000
#define UART_BAUDRATE 115200
#define REFERENCE_CLOCK_Hz 15*1000*1000
#define UART_BAUDRATE 9600
#define TARGET_PYNQ_Z2 1

/**
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