Add broadcast mode to DMA

hw/core-v-mini-mcu/ao_peripheral_subsystem.sv

@@ -118,7 +118,10 @@ module ao_peripheral_subsystem
 
     // EXTERNAL PERIPH
     output reg_req_t ext_peripheral_slave_req_o,
-    input  reg_rsp_t ext_peripheral_slave_resp_i
+    input  reg_rsp_t ext_peripheral_slave_resp_i,
+
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -364,13 +367,15 @@ module ao_peripheral_subsystem
       .intr_timer_expired_1_0_o(rv_timer_1_intr_o)
   );
 
-  parameter DMA_TRIGGER_SLOT_NUM = 5;
+  parameter DMA_TRIGGER_SLOT_NUM = 7;
   logic [DMA_TRIGGER_SLOT_NUM-1:0] dma_trigger_slots;
   assign dma_trigger_slots[0] = spi_rx_valid;
   assign dma_trigger_slots[1] = spi_tx_ready;
   assign dma_trigger_slots[2] = spi_flash_rx_valid;
   assign dma_trigger_slots[3] = spi_flash_tx_ready;
   assign dma_trigger_slots[4] = i2s_rx_valid_i;
+  assign dma_trigger_slots[5] = ext_dma_slot_tx_i;
+  assign dma_trigger_slots[6] = ext_dma_slot_rx_i;
 
   dma #(
       .reg_req_t (reg_pkg::reg_req_t),

hw/core-v-mini-mcu/core_v_mini_mcu.sv

@@ -315,7 +315,10 @@ module core_v_mini_mcu
     output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
 
-    output logic [31:0] exit_value_o
+    output logic [31:0] exit_value_o,
+
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -628,7 +631,9 @@ module core_v_mini_mcu
       .uart_intr_rx_parity_err_o(uart_intr_rx_parity_err),
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
-      .ext_peripheral_slave_resp_i
+      .ext_peripheral_slave_resp_i,
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (

hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl

@@ -69,7 +69,10 @@ ${pad.core_v_mini_mcu_interface}
     output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
 
-    output logic [31:0] exit_value_o
+    output logic [31:0] exit_value_o,
+
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -380,7 +383,9 @@ ${pad.core_v_mini_mcu_interface}
       .uart_intr_rx_parity_err_o(uart_intr_rx_parity_err),
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
-      .ext_peripheral_slave_resp_i
+      .ext_peripheral_slave_resp_i,
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (

hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv

@@ -191,7 +191,9 @@ module xilinx_core_v_mini_mcu_wrapper
       .pdm2pcm_pdm_io,
       .i2s_sck_io(i2s_sck_io),
       .i2s_ws_io(i2s_ws_io),
-      .i2s_sd_io(i2s_sd_io)
+      .i2s_sd_io(i2s_sd_io),
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i,
   );
 
   assign exit_value_o = exit_value[0];

hw/ip/dma/data/dma.hjson

@@ -25,6 +25,14 @@
         { bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" }
       ]
     },
+    { name:     "DST_BCST_PTR",
+      desc:     "Broadcast output data pointer (word aligned)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" }
+      ]
+    },
     { name:     "ADDR_PTR",
       desc:     "Addess data pointer (word aligned)",
       swaccess: "rw",
@@ -68,6 +76,11 @@
           name: "DST_PTR_INC", 
           desc: "Destination pointer increment",
           resval:4
+        },
+        { bits: "23:16", 
+          name: "BCST_PTR_INC", 
+          desc: "Broadcast pointer increment",
+          resval:4
         }
       ]
     },
@@ -87,6 +100,22 @@
         }
       ]
     },
+    { name:     "BSLOT",
+      desc:     '''The DMA will wait for the signal 
+                   connected to the selected trigger_slots to be high
+                   on the read and write side respectivly''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "15:0", name: "BX_TRIGGER_SLOT",
+          desc: "Broadcast slot selection mask"
+        },
+        { bits: "31:16", name: "DX_TRIGGER_SLOT",
+          desc: "Dummy slot selection mask"
+        }
+      ]
+    },
     { name:     "DATA_TYPE",
       desc:     '''Width/type of the data to transfer''',
       swaccess: "rw",
@@ -115,6 +144,7 @@
             { value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"},
             { value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"},
             { value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"},
+            { value: "3", name: "BROADCAST_MODE" , desc: "Equivalent to LINEAR_MODE but writing at two destinations simultaneously"},
           ]
         }
       ]